DETAILED ACTION
This action is responsive to 01/08/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Objections
Claim 8 is objected to because of the following informalities: In line 1, insert “wherein” after “claim 1,”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, and 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Murakami et al. (US Pub. 2014/0313174), hereinafter Murakami, in view of Chen et al. (US Pub. 2024/0265873), hereinafter Chen.
Regarding claim 1, Murakami discloses a driving circuit comprising a plurality of stages (see fig. 1 and [0066]-a plurality of shift register units SR), wherein each of the plurality of stages comprises: a first transistor connected to a first terminal (transistor P4 connected to input terminal INB-see fig. 6), to which a start signal is input (start pulse ST is applied to input IN (INB)-see figs. 1 and 6) and a first node (node Q-see fig. 6), wherein the first transistor includes a gate connected to a clock terminal, to which a clock signal is input (gate of P4 is connected to clock signal CKBb-see fig. 6); a pull-up transistor connected to a second terminal, to which a first voltage is supplied (P5 connected to VDD-see fig. 6), and an output terminal (output terminal OB-see fig. 6); a pull-down transistor connected to the output terminal and a third terminal (N5 and P3 having a common terminal in which clock signal CKBa is applied); and a control circuit connected to the first node (inverter (P1, N2) and inverter (P2, N3) are connected to node Q and herein equated to claimed control circuit-see fig. 6), a gate of the pull-down transistor, and a gate of the pull-up transistor (as shown in fig. 6, node Q is connected to gate of P5 (pull-up transistor) and gate of N5 of the pull-down transistor), wherein the control circuit controls a voltage of the gate of the pull-down transistor and a voltage of the gate of the pull-up transistor based on a voltage of the first node (i.e., P5 and N5 are controlled by voltage at node Q-see fig. 6), wherein the pull-down transistor comprises a first sub-transistor (P3-see fig. 6) and a second sub-transistor (N5-see fig. 6) connected in parallel with each other (see fig. 6), wherein conductivity types of the first sub-transistor and the second sub-transistor are different from each other (P-channel transistor P3 and N-channel transistor N5-see fig. 6), wherein a gate of the second sub-transistor and the gate of the pull-up transistor are connected to a same node (i.e., gate of P5 and gate of N5 are both connected to node Q-see fig. 6).
Murakami does not appear to expressly disclose a pull-down transistor connected to a third terminal to which a second voltage less than the first voltage is supplied.
Chen is relied upon to teach a pull-down transistor connected to a third terminal to which a second voltage less than the first voltage is supplied (see fig. 3 and [0136], wherein a terminal of pull up transistor T17 is couple to first voltage line (high voltage) VGH while a terminal of pull-down transistor T18 is coupled to a second voltage line (low voltage) VGL).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Chen with the invention of Murakami such that one terminal of a pull-up transistor is connected to a terminal in which a first voltage is applied, and a terminal of a pull-down transistor is connected to another terminal to which a second voltage less than the first voltage is applied, as taught by Chen, therefore, an output circuit (1003) is configured to write the first voltage signal provided by the first voltage line VGH or the second voltage signal provided by the second voltage line VGL into the output terminal OUT as an output signal under control of a first output control signal or a second output control signal (see [0125]).
Regarding claim 2, Murakami discloses wherein the first sub-transistor is a P-channel transistor (P-channel transistor P3-see fig. 6 and [0072]), and the second sub-transistor is an N-channel transistor (N-channel transistor N5-see fig. 6 and [0072]).
Regarding claim 9, Chen is further relied upon to teach wherein, while a low-level output signal is output from the output terminal in a low-frequency driving mode, the clock signal input to the clock terminal is a high-level signal (see, for example, [0170]-when the display panel is in low-frequency display mode, it is necessary to set clock signal (CK) high in a data holding phase (at this time, the output of the gate driving circuit needs to be kept at a low level) to reduce overall power consumption of the gate driving circuit).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Chen with the invention of Murakami such that while a low-level output signal is output from the output terminal in a low-frequency driving mode, the clock signal input to the clock terminal is a high-level signal, which, as taught by Chen, to reduce overall power consumption of the gate driving circuit (see [0170]).
Regarding claim 10, Murakami discloses wherein the start signal is an external signal or a signal output from an output terminal of a previous stage (see fig. 1 with description in [0018]-start pulse ST).
Claim 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Murakami in view of Chen, and further in view of Kim et al. (US Patent 10,706,784), hereinafter Kim.
Regarding claim 8, Murakami in view of Chen does not appear to expressly teach wherein, the clock signal is a first clock signal or a second clock signal, wherein the first clock signal and the second clock signal are signals in which a high-level voltage and a low-level voltage are alternate, and the second clock signal is a signal shifted by a half cycle from the first clock signal, and wherein the first clock signal is input to the clock terminal of each of odd-numbered stages among the plurality of stages, and the second clock signal is input to the clock terminal of each of even-numbered stages among the plurality of stages.
Kim is relied upon to teach wherein, the clock signal is a first clock signal or a second clock signal, wherein the first clock signal and the second clock signal are signals in which a high-level voltage and a low-level voltage are alternate, and the second clock signal is a signal shifted by a half cycle from the first clock signal, and wherein the first clock signal is input to the clock terminal of each of odd-numbered stages among the plurality of stages, and the second clock signal is input to the clock terminal of each of even-numbered stages among the plurality of stages (see fig. 2 with description in [col. 5, ll. 56-col. 6, ll. 10]-each of odd-numbered stage circuits ST1, ST3, … may be supplied with the first clock signal CLK1 … each of even-numbered stage circuits ST2, ST4, … may be supplied with the second clock signal CLK2, … the second clock signal CLK2 has the same high level and low level periods as those of the first clock signal CLK1 and is provided with a ½-cycle phase difference relative to the first clock signal CLK1 ([col. 6, ll. 5-10])).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Kim with the inventions of Murakami and Chen the first clock signal is input to the clock terminal of each of odd-numbered stages among the plurality of stages, and the second clock signal is input to the clock terminal of each of even-numbered stages among the plurality of stages, as taught by Kim, which constitutes combining prior art elements according to known methods to yield predictable results.
Allowable Subject Matter
Claims 3-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The references of record fail to teach or suggest “wherein each of the plurality of stages further comprises a first capacitor connected to the output terminal and a second node, to which a gate of the first sub-transistor is connected”, as recited in claim 3. Claims 4-7 depend from and recite limitations that further narrow claim 3, and are therefore equally indicated as allowable.
Claims 11-20 allowed.
The following is an examiner’s statement of reasons for allowance: The references of record fail to teach or suggest the circuit structure recited in claim 11, specifically, the references of record fail to teach or suggest “a third transistor connected to a third node and a third terminal, to which a second voltage greater than the first voltage is supplied, wherein the third transistor includes a gate connected to the first node; a fourth transistor connected to the third node and the second terminal, wherein the fourth transistor includes a gate connected to the second node; a fifth transistor connected to the third terminal and an output terminal, wherein the fifth transistor includes a gate connected to the third node”.
Claims 12-20 depend from and recite limitations that further narrow claim 11, and are therefore equally allowed.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARDIS F AZONGHA whose telephone number is (571)270-7706. The examiner can normally be reached 10AM-7:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at (571)272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SARDIS F AZONGHA/ Primary Examiner, Art Unit 2627