DETAILED ACTION
General Remarks
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3. When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
5. Applicants seeking an interview with the examiner, including Microsoft Team Meeting, are encouraged to fill out the online Automated Interview Request (AIR) form
(https://www.uspto.gov/sites/default/files/documents/PTOL413A.pdf). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
6. Status of claim(s) to be treated in this office action:
a. Independent: 1, 15 and 16.
b. Pending: 1-20.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 15, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Htoo PG PUB 20110018617 (hereinafter Htoo), in view of Rana PG PUB 20220158552 (hereinafter Rana).
Regarding independent claim 1, Htoo teaches a voltage generation circuit (301/303/305 in figure 3 of Htoo) comprising:
a clock voltage doubling circuit (303 in figure 3 of Htoo); and a charge pump circuit (305 in figure 3 of Htoo),
But Htoo does not teach a clock voltage doubling circuit comprising a first signal generation circuit, a second signal generation circuit and a first output circuit wherein: the first signal generation circuit is connected with a first electrode and a second electrode of a metal oxide semiconductor (MOS) transistor in the first output circuit, the second signal generation circuit is connected with a third electrode of the MOS transistor in the first output circuit, and the second electrode of the MOS transistor in the first output circuit is connected with the charge pump circuit; the first signal generation circuit is configured to apply a positive voltage signal to the first electrode of the MOS transistor in the first output circuit and apply a source voltage signal to the second electrode of the MOS transistor in the first output circuit under control of an input first clock signal; the second signal generation circuit is configured to apply a second clock signal different from the input first clock signal to the third electrode of the MOS transistor in the first output circuit under the control of the input first clock signal; and the first output circuit is configured to output a voltage doubling clock signal to the charge pump circuit under control of the second clock signal.
However, Rana teaches in figures 2A, 4A, 4C-7C a clock voltage doubling circuit comprising a first signal generation circuit (positive/negative bootstrapping circuit in figure 2A/4A of Rana, e.g., 305n in figure 4A/4C, MN1/MN2/Cbs1/Cbs2 in figure 2A of Rana, 405p/405n in figure 6A of Rana), a second signal generation circuit (switching circuit 310p or 312p in figure 4C of Rana) and a first output circuit (322p or 320p in figure 4C of Rana) wherein: the first signal generation circuit (305n in figure 4A/4C of Rana) is connected with a first electrode (NC1 in figure 4A of Rana) and a second electrode (304 in figure 4A of Rana) of a metal oxide semiconductor (MOS) transistor (MP1 in figure 4C of Rana) in the first output circuit (322p or 320p in figure 4C of Rana), the second signal generation circuit (switching circuit 310p or 312p in figure 4 of Rana ) is connected with a third electrode (NB1 in figure 4A of Rana) of the MOS transistor in the first output circuit (322p or 320p in figure 4C of Rana), and the second electrode of the MOS transistor (MP1 in figure 4C of Rana) in the first output circuit is connected with the charge pump circuit (the remainder of positive charge circuit 300p, including the output node 304/Vpos and load 307 in figure 4Av);
the first signal generation circuit (positive/negative bootstrapping circuit in figure 2A/4A, e.g., 305n in figure 4A/4C of Rana, MN1/MN2/Cbs1/Cbs2 in figure 2A of Rana, 405p/405n in figure 6A of Rana) is configured to apply a positive voltage signal to the first electrode of the MOS transistor in the first output circuit (320p in figure 4C of Rana) and apply a source voltage signal to the second electrode (304 in figure 4A of Rana) of the MOS transistor in the first output circuit under control of an input first clock signal (CK1N in figure 4A of Rana);
the second signal generation circuit (switching circuit 310p or 312p in figure 4 of Rana ) is configured to apply a second clock signal (NB1 gate drive signal in figure 4A of Rana) different from the input first clock signal (CK1N in figure 4A of Rana) to the third electrode of the MOS transistor (MP1 in figure 4C of Rana) in the first output circuit under the control of the input first clock signal; and the first output circuit (322p or 320p in figure 4C of Rana) is configured to output a voltage doubling clock signal to the charge pump circuit under control of the second clock signal (MP1 in 320p selectively transfers the boosted voltage from NC1 to output nde 304/Vpos in figure 4A of Rana, transfer is controlled by NB1 from switching circuit 310p).
Rana teaches a positive charge-pump circuit 310p having a positive boost-strapped charge-pump circuit 305p, gate signal switching circuits 310p/312p, and output charge-transfer branches 320p/322p. It would have been obvious to a person having ordinary skill in the art, before the effective filing date, to implement the clock booster 303 of Htoo using Rana’s boosted gate-drive, level shifting and charge transfer transistor arrangement. As both references concern the same problem: efficiently generating boosted clock voltages for operating charge-pump circuitry while reducing transistor resistance and power loss. The combination of Htoo and Rana would increase the gate overdrive of the clock-output transistor, and reduce charge transfer resistance, by substituting Rana’s known transistor-level implementation for the clock-booster block already expressly required by Htoo.
Regarding claim 2, the combination of Htoo and Rana teaches the voltage generation circuit of claim 1, wherein a high level voltage of the voltage doubling clock signal is the same as a voltage of the positive voltage signal, and a low level voltage of the voltage doubling clock signal is the same as a voltage of the source voltage signal (Rana teaches in figure 2B/4B clock and boosted-node levels, NC1/NC2 alternate between source related voltage and a boosted positive voltage, [0026]-[0031]).
Regarding independent claim 15, claim 15 recites claim 1 within a memory device having a memory-cell array and a peripheral circuit coupled to the array (figure 3 and figure 4 of Htoo show the clock booster and charge pump coupled to WLs).
Regarding independent claim 16, claim 16 recites claim 1 within a memory device having one or more memory devices and a controller coupled to and controlling the memory device (Htoo teaches the internal memory device voltage generation circuitry. A controller couples to one or more flash memory devices was conventional).
Allowable Subject Matter
Claims 3-14, 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The closest prior arts to the present invention are Htoo PG PUB 20110018617 and RANA 20220158552.
Htoo discloses a charge pump circuit for generating an output voltage. Charge pump circuits typically have two branches. As the clocks supplying the branches of a charge pump circuit alternate, the output of each branch will alternately provide an output voltage, which are then combined to form the pump output. The techniques described here allow charge to be transferred between the two branches, so that as the capacitor of one branch discharges, it is used to charge up the capacitor in the other branch. An exemplary embodiment using a voltage doubler-type of circuit, with the charge transfer between the branches accomplished using a switch controller by a boosted version of the clock signal, which is provided by a one-sided voltage doubler.
Rana teaches the charge transfer transistors of a positive or negative charge pump are biased at their gate terminals with a control voltage that provides for an higher level of gate-to-source voltage in order to reduce switch resistance in passing a boosted (positive or negative) voltage to a voltage output of the charge pump. This control voltage is generated using a bootstrapping circuit whose polarity of operation (i.e., negative or positive) is opposite to a polarity (i.e., positive or negative) of the charge pump.
Regarding claim 3 (and the respective dependent claims), the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: wherein a first port of the first signal generation circuit is connected with the first electrode of the MOS transistor in the first output circuit, and a second port of the first signal generation circuit is connected with the second electrode of the MOS transistor in the first output circuit; the MOS transistor in the first output circuit is configured to: output a high level voltage of the voltage doubling clock signal through the second electrode of the MOS transistor in the first output circuit when the second clock signal applied to the third electrode of the MOS transistor in the first output circuit is at a low level; and output a low level voltage of the voltage doubling clock signal through the second electrode of the MOS transistor in the first output circuit when the second clock signal applied to the third electrode of the MOS transistor in the first output circuit is at a high level; and wherein a voltage of the second clock signal at the low level is greater than a voltage of the source voltage signal.
Regarding claim 17 (and the respective dependent claims), the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: wherein a first port of the first signal generation circuit is connected with the first electrode of the MOS transistor in the first output circuit, and a second port of the first signal generation circuit is connected with the second electrode of the MOS transistor in the first output circuit; the MOS transistor in the first output circuit is configured to: output a high level voltage of the voltage doubling clock signal through the second electrode of the MOS transistor in the first output circuit when the second clock signal applied to the third electrode of the MOS transistor in the first output circuit is at a low level; and output a low level voltage of the voltage doubling clock signal through the second electrode of the MOS transistor in the first output circuit when the second clock signal applied to the third electrode of the MOS transistor in the first output circuit is at a high level; and wherein a voltage of the second clock signal at the low level is greater than a voltage of the source voltage signal.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIAOCHUN L CHEN whose telephone number is (571)272-0941. The examiner can normally be reached on M-F: 9AM-5:00PM.
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/XIAOCHUN L CHEN/Examiner, Art Unit 2824
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