DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-25 of U.S. Patent No. 12,205,627. Although the claims at issue are not identical, they are not patentably distinct from each other because at least as show in a table below.
Instant app
12,205,627
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464
870
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Greyscale
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406
392
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Greyscale
Claim 16/21, 4, 10, 18, 19
Claim 1
Claim 5
Claim 24
Claim 6, 20
Claim 7
Claim 7/8
Claim 8
Claim 3/9
Claim 4
Claim 11
Claim 2
Claim 12
Claim 5
Claim 13/14
Claim 9
Claim 15
Claim 4
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 4-6, 8, 10-12, 15-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iwai et al. (PGPUB 20100157693), hereinafter as Iwai.
Regarding claim 2, Iwai teaches a host system, comprising:
one or more interfaces (Fig 1E, circuits 5 and its connections) comprising one or more signal paths (connections) operable for communications with one or more memory systems; and
processing circuitry (Fig 1E, circuit 5, although not a separate unit, but it has been ruled that mere constructing a formely integral structure in various elements involves only routine skill in the art. Nerwin v. Erlichman, 168 USPQ 177, 179) coupled with the one or more interfaces and configured to cause the host system to:
receive an indication that a system that includes the host system is powering down (Fig. 16a, S202, it is well known that a low-voltage mode is a power down mode); and
transmit, in response to the indication that the system is powering down, a command ([0149] a signal is activated) that configures a memory system of the one or more memory systems to reprogram data from one or more first blocks of non-volatile memory cells of the memory system to one or more second blocks of non-volatile memory cells of the memory system ([0196]).
Regarding claim 3, Iwai teaches switch from a first mode of operation to a second mode of operation in response to the indication that the system is powering down, wherein the second mode of operation supports a reduced set of operations compared to the first mode of operation (Fig 16A, low-capacity mode).
Regarding claim 4, Iwai teaches switch, in response to the indication that the system is powering down, from a first power usage by the host system to a second power usage by the host system that is less than the first power usage (Fig 16a, low voltage mode is known as low power mode).
Regarding claim 5, Iwai teaches the processing circuitry is further configured to cause the host system to: supply, from a power source, a first power to the memory system, a first voltage to the memory system, or both prior to reception of the indication that the system is powering down; and supply, from the power source, a second power to the memory system that is less than the first power, a second voltage to the memory system that is less than the first voltage, or both in response to the indication that the system is powering down (Fig 16a).
Regarding claim 6, Iwai teaches detect an ambient temperature of the host system, wherein the command that configures the memory system to reprogram the data is transmitted in response to the ambient temperature satisfying a threshold temperature ([0047], and the examiner is taking note that it is well known in the field that a temperature control comprising a threshold temperature value).
Regarding claim 8, Iwai teaches receive, from the memory system, an indication of the threshold temperature (Fig 1E).
Regarding claim 10, Iwai teaches receive an indication that an engine of the system is turning off, that a power source of the system is switching from a high power state to a low power state, or both (Fig 16A/16B).
Regarding claim 11, Iwai teaches receive an indication of a refresh capability of the memory system, wherein the command that configures the memory system to reprogram the data is transmitted in response to the refresh capability of the memory system ([0181]).
Regarding claim 12, Iwai teaches to reprogram the data is transmitted in response to a time elapsed, since reception of the indication that the system is powering down, satisfying a threshold (Fig 23B, tREF_M).
Regarding claim 15, Iwai teaches to reprogram the data from multiple-level memory cells of the one or more first blocks to multiple-level memory cells of the one or more second blocks while a temperature associated with the memory system satisfies a threshold ([0196]).
Regarding claim 16, Iwai teaches a non-transitory computer-readable medium storing code comprising instructions which, when executed by processing circuitry of a host system, cause the host system to:
receive an indication that a system that includes the host system is powering down (Fig. 16a, S202, it is well known that a low-voltage mode is a power down mode); and
transmit, in response to the indication that the system is powering down, a command that configures a memory system to reprogram data from one or more first blocks of non-volatile memory cells of the memory system to one or more second blocks of non-volatile memory cells of the memory system ([0196]).
Regarding claim 17, argument used in rejection of claim 3 applies.
Regarding claim 18, argument used in rejection of claim 4 applies.
Regarding claim 19, Iwai teaches non-transitory computer-readable medium of The non-transitory computer-readable medium of wherein the instructions, when executed by the processing circuitry of the host system, further cause the host system to:
supply, from a power source, a first power to the memory system, a first voltage to the memory system, or both prior to reception of the indication that the system is powering down ([0196]); and
supply, from the power source, a second power to the memory system that is less than the first power, a second voltage to the memory system that is less than the first voltage, or both in response to the indication that the system is powering down ([0196]).
Regarding claim 20, Iwai teaches detect an ambient temperature of the host system, wherein the command that configures the memory system to reprogram the data is transmitted in response to the ambient temperature satisfying a threshold temperature (reasoning in rejection of claim 6 applies).
Regarding claim 21, Iwai teaches a method by a host system, comprising:
receiving an indication that a system that includes the host system is powering down; and transmitting, in response to the indication that the system is powering down, a command that configures a memory system to reprogram data from one or more first blocks of non-volatile memory cells of the memory system to one or more second blocks of non-volatile memory cells of the memory system (argument/reasoning of rejection of claim 1 applies).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iwai, in view of Jang et al. (PGPUB 20230125869), hereinafter as Jang.
Regarding claim 7, Iwai teaches a system as in rejection of claim 6,
But not expressly a temperature range,
Jung teaches the ambient temperature satisfying the threshold temperature comprises the ambient temperature being within a target temperature range for programming data to the memory system ([0069]).
Since Jung and Iwai are both from the same field of semiconductor memory device, the purpose disclosed by Jung would have been recognized in the pertinent art of Iwai.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to use a defined temperature range as in Jung into the device of Iwai for the purpose of ensuring performance of the memory device as temperature changes.
Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iwai, in view of Wang et al. (PGPUB 20220118879), hereinafter as Wang.
Regarding claim 13, Iwai teaches a system as in rejection of claim 2,
But not expressly power down mode associated with a shut down.
Wang teaches transmit, after transmission of the command that configures the memory system to reprogram the data and in response to the indication that the system is powering down, a command initiating a shut down of the memory system (Fig 1).
Since Wang and Iwai are both from the same field of semiconductor memory device, the purpose disclosed by Wang would have been recognized in the pertinent art of Iwai.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to use low power mode as in Wang into the device of Iwai for the purpose of proper power down sequence of the system.
Regarding claim 14, Iwai teaches transmit, an indication to switch the memory system from a first mode corresponding to a first power usage by the memory system to a second mode corresponding to a second power usage by the memory system that is lower than the first power usage (Fig 16A),
Wang teaches before transmission of the command that configures the memory system to reprogram the data and in response to the indication that the system is powering down (Fig 1).
The reason for combining the references used in rejection of claim 13 applies.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIN HUANG whose telephone number is (571)270-5798. The examiner can normally be reached M-F 9-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MIN HUANG/ Primary Examiner, Art Unit 2827
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