DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, lines 7-8 of the claim recite “forming an anode and a cathode over each of the plurality of semiconductor layers to form a plurality of light emitting elements”. In a plain reading of the limitation, it would appear that the claim is stating that an anode and a cathode is formed over all of the semiconductor layers of the light emitting element. However, as best understood from the instant application, page 9 describes the semiconductor layer as being all of the n-type cladding layer, the emission layer, and the p-type cladding layer, but the cathode is only formed over the n-type cladding layer (see cathode 120 over n-type cladding layer 112 in Fig. 1). As a result, it is unclear as to how both the anode and the cathode are formed over the plurality of semiconductor layers when the anode is formed over all of the layers (by being formed on the p-type cladding layer) but the cathode is not (by being formed on the n-type cladding layer). Clarification is required. For purposes of examination, the examiner will interpret the anode as being formed on the p-type layer and the cathode as being formed on the n-type layer.
As for claim 2, the claim depends on claim 1, and sets forth further limitations of both the photoluminescence measurement and the electroluminescence measurement. However, claim 1 only requires that one of the photoluminescence property or the electroluminescence property be measured, as the examiner read “at least one of . . . or” to mean that the claim only requires acquiring either the photoluminescence property or the electroluminescence property, not both. As a result, it is unclear if claim 2 is only setting forth further limitations of the acquisition of the photoluminescence property and the electroluminescence property and that only one of those properties has to actually be measured extending from claim 1, or if claim 2 requires both the photoluminescence property and the electroluminescence property to be measured by the use of the word “and” between the photoluminescence and electroluminescence descriptions. Clarification is required. For purposes of examination, the examiner will interpret the claim to only require one of the photoluminescence or electroluminescence properties from its dependence on claim 1.
The above explanation holds for all of claims 4-6 which depend on claim 2.
Claim 7 recites the limitation "the inorganic semiconductor" in line 4 of the claim. There is insufficient antecedent basis for this limitation in the claim. While claim 1 recites “an organic semiconductor”, it also recites that each of the n-type cladding layer, the emission layer, and the p-type cladding layer include an inorganic semiconductor. As a result, it is unclear which “inorganic semiconductor” is being referred to in claim 7. Is it the entire inorganic semiconductor of the n-type layer, the emission layer, and the p-type layer? Or can it be any one of those layers? And if so, which of the layers is it?
Claim 13 recites the limitation “in a direction of the row or the column" in lines 2-3 of the claim. There is insufficient antecedent basis for this limitation in the claim. While claim 1 recites rows and columns, the claim sets forth “a matrix form having a plurality of rows and a plurality of columns”. As a result, it is unclear which of the plurality of rows or plurality of columns is being referred to by “the row or the column” in this claim.
Claims 3, 8-12, and 14 are rejected by virtue of their dependence on at least claim 1, thereby containing all the limitations of the claims on which they depend.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4-6, 10, 11, 13, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura (2024/0178073) in view of Yoshino et al (JP 6723484) and in further view of Matsumura et al (JP 2015010834), as best understood by the examiner.
The examiner notes that citations for Yoshino and Matsumura are taken from the provided English translation.
Regarding claim 1, Nakamura (Figs. 1 and 3-5) discloses a method for inspecting a light-emitting element, the method comprising forming a buffer layer 402 over a substrate (sapphire substrate 401); forming, over the buffer layer, an n-type cladding layer 403, an emission layer 404, and a p-type cladding layer 405, the n- and p-type layers being inorganic (GaN, disclosed in paragraph 0038, is an inorganic semiconductor) to form a plurality of semiconductor layers arranged in a matrix form having a plurality of rows and a plurality of columns (see paragraph 0028 with sample S; see also the inset of Fig. 5); forming an anode 407B and a cathode 407A (see Fig. 4e and paragraph 0041-0042) over each of the plurality of semiconductor layers to form a plurality of light-emitting elements; and acquiring a photoluminescence property of the plurality of light emitting elements before forming the anode and the cathode (the PL measurement is performed with inspection device 1 featuring a single detector 82 before formation of the pad that forms the anode and the cathode as seen in Fig. 5 and described in paragraphs 0044-0045), wherein the buffer layer has a function to promote crystallization of the semiconductor layers (inherent to a buffer layer in a semiconductor).
Nakamura fails to disclose that the substrate is amorphous, and that the photoluminescence property is acquired by a first and a second detector.
Yoshino, in a semiconductor light emitting device, discloses (Figs. 3 and 7) a light emitting element where each pixel includes a glass substrate 111 (see paragraph 0030), with gas being known to be amorphous. Yoshino also discloses the light emitting device to have a buffer layer 113, an n-type GaN layer 114, an emissive layer 115, a p-type GaN layer 116 (see paragraph 0030), with each of the n-type, emissive, and p-type layers being an inorganic semiconductor (see paragraph 0034), along with an anode 120 and a cathode 118, and the buffer layer promotes crystallization (the device has high crystallinity as in paragraph 0035).
Matsumura, in an inspection device for inspecting light-emitting elements, discloses measuring LED chips in a semi-finished state but while they still have a photoluminescence property (see paragraph 0027). Matsumura performs the measurement (see Fig. 1) using a first detector 21 and a second detector 26 (see paragraph 0019).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to substitute the substrate of Nakamura with an amorphous substrate as taught by Yoshino and to add an additional detector to the inspection device of Nakamura to perform the photoluminescence acquisition as taught by Matsumura, the motivation being that an amorphous substrate allows for better thermal protection for the light-emitting elements, while using multiple detectors allows for improved measurement of various aspects of the plurality of light-emitting elements as it allows for discrete measurement of different wavelengths of light emitted by the semiconductor with each camera (see paragraph 0020), thereby increasing throughput of measurement (see paragraph 0008).
As for claim 2, Matsumura further discloses that the acquisition of the photoluminescence property comprises (see Fig. 1) irradiating a first element group including two or more light-emitting elements selected from the plurality of light-emitting elements with light 71 from source 7 and measuring photoluminescence of the light-emitting elements included in the first element group with the first detector 21 (see paragraph 0020, “In addition, the first observation unit 2A is provided with a long pass filter 23 for transmitting light of a wavelength longer than the first wavelength which is a reference wavelength. That is, the observation camera 21 can observe the light 29 a which has passed through the long pass filter 23 among the part 72 a of the light emitted from the LED chip C”); and irradiating a second element group including two or more light-emitting elements selected from the plurality of light-emitting elements with light 71 from source 7 and measuring photoluminescence of the light-emitting elements included in the second element group with the second detector 26 (see paragraph 0020, “n the other hand, the second observation unit 2B is provided with a short pass filter 28 for transmitting light of a wavelength longer than the second wavelength which is a reference wavelength. That is, the observation camera 26 can observe the light 29 b that has passed through the short pass filter 28 in the portion 72 b of the light emitted from the LED chip C”).
As for claim 4, Matsumura further discloses that at least one light-emitting element among the plurality of light emitting elements is included in both the first and second elements groups (they are part of LED chip C as in paragraph 0020), but fails to disclose calibrating the first and second detectors using the photoluminescence of the at least one light-emitting element.
However, the examiner takes Official notice as to the well known practice of performing calibration via a control measurement. The examiner interprets the shared light-emitting element in the above situation to be the control element that is being measured, and therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to calibrate the first and second detectors of the combination of Nakamura, Yoshino, and Matsumura, the motivation being to ensure the device performing the measurements is in proper working order to obtain accurate results.
As for claims 5 and 6, claims 1 and 2, the claim on which claims 5 and 6 depend, includes measuring either the photoluminescence property or the electroluminescence property in the alternative (see claim 1) and specifics thereof (see claim 2). In the rejection set forth above for claim 1, the examiner interpreted that claim to read on the scenario where the photoluminescence property is measured. Once one alternative condition has been met, the entire claim is rejected. Since that alternative condition has been satisfied, the entire alternative claim limitation is also rejected. As a result, any further limitations directed to an alternative that was not treated in claim 1, which in this case are limitations directed to measurement of the electroluminescence property, similarly stands rejected As a result, claims 5 and 6 are rejected due to the alternative limitation in claim 1, which sets forth that the photoluminescence property of the plurality of light-emitting elements is acquired, being satisfied. Further regarding claim 6, the examiner notes the discussion of first and second light-emitting elements above regarding claim 2.
As for claim 10, the combination of Nakamura, Yoshino, and Matsumura discloses the claimed invention as set forth above regarding claim 1. While the combination fails to disclose that the first and second detector are configured so that a distance from the amorphous substrate and/or an angle with respect to the amorphous substrate can be adjusted, Matsumura teaches the idea of adjustability as the inspection apparatus places the LED chip W in predetermined positions via an XY stage that can move the wafer in the X and Y directions relative to the detectors as needed (see paragraph 0026).
As a result, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to move the detectors of the combination relative to the amorphous substrate as suggested by moving the substrate relative to the detectors in Matsumura, the motivation being that the provision of adjustability, where needed, involves only routine skill in the art. In re Stevens, 101 USPQ 284 (CCPA 1954).
As for claims 11, 13, and 14, claim 1, the claim on which claim 11 depends, includes measuring either the photoluminescence property or the electroluminescence property in the alternative. In the rejection set forth above for claim 1, the examiner interpreted that claim to read on the scenario where the photoluminescence property is measured. Once one alternative condition has been met, the entire claim is rejected. Since that alternative condition has been satisfied, the entire alternative claim limitation is also rejected. As a result, any further limitations directed to an alternative that was not treated in claim 1, which in this case are limitations directed to measurement of the electroluminescence property, similarly stands rejected As a result, claim 11 is rejected due to the alternative limitation in claim 1, which sets forth that the photoluminescence property of the plurality of light-emitting elements is acquired, being satisfied. Claims 13 and 14 are rejected by virtue of their dependence on claim 1.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura (2024/0178073) in view of Yoshino et al (JP 6723484) and in further view of Matsumura et al (JP 2015010834 and in further view of Ma (2007/0170933).
As for claim 3, the combination of Nakamura, Yoshino, and Matsumura discloses the claimed invention as set forth above regarding claim 1, but fails to disclose acquiring both the photoluminescence property and the electroluminescence property.
Ma, in a method for evaluating light-emitting materials, discloses, in Fig. 5, that a light injection means 70 can be incorporated into the method to allow for measurement of photoluminescence using the same optical measurement means 40 that are used to measure the electroluminescence of the LED device in the sample 20 (see paragraph 0029).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to perform both photoluminescence and electroluminescence measurements in the combination of Nakamura, Yoshino, and Matsumura as taught by Ma, the motivation being that Ma shows the capability of performing both photoluminescence and electroluminescence measurements with the same optical measuring means (see paragraph 0029), thereby simplifying operation of testing of the light emitting material.
Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura (2024/0178073) in view of Yoshino et al (JP 6723484) and in further view of Matsumura et al (JP 2015010834 and in further view of Omi et al (JP 2010239041).
As for claim 7, the combination of Nakamura, Yoshino, and Matsumura discloses the claimed invention as set forth above regarding claim 1 but fail to disclose forming, over the amorphous substrate, a plurality of alignment marks for alignment of the first and second detectors, wherein the plurality of alignment marks includes the organic semiconductor.
Omi, in a semiconductor inspection device, discloses the use of a plurality of alignment marks 12 on wafer 10 (see Fig. 3a for example); these marks can also include marks 12a as part of the semiconductor chip (see Fig. 3b) which would make the alignment marks part of the inorganic semiconductor of the combination disclosed above (see paragraphs 0027 and 0028), with the alignment marks serving as references that indicate position coordinates of the chips or patterns on the wafer (see paragraph 0031). The alignment marks allow for alignment of the detectors as is disclosed by imaging of the mark with the inspection camera of the imaging unit of Omi (see paragraph 0057).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to add alignment marks to the substrate of the light emitting element of Nakamura, Yoshino, and Matsumura as taught by Omi, the motivation being that alignment marks ensure that the wafer is in the correct position in relation to the detectors (see paragraph 0059 of Omi for example), thereby increasing accuracy of any measurements being made.
As for claim 8, Omi further discloses that the plurality of alignment marks are formed outside a region in which the plurality of light-emitting elements is arranged (see Fig. 3a of Omi showing the alignment marks outside of the circuits 13; these circuits are the equivalents of the light emitting elements in the combination).
As for claim 9, Omi further discloses that the plurality of alignment marks are formed between adjacent light emitting elements (see Fig. 3d, showing alignment marks 12a between circuit portions 14; these circuits are the equivalents of the light emitting elements in the combination).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura (2024/0178073) in view of Yoshino et al (JP 6723484) and in further view of Matsumura et al (JP 2015010834 and in further view of Stokes et al (2003/0122561).
As for claim 12, the combination of Nakamura, Yoshino, and Matsumura discloses the claimed invention as set forth above regarding claim 1, but fails to disclose that the n-type cladding layer continues between adjacent light-emitting elements.
Stokes, in a method for evaluating properties of semiconductor materials, discloses (see Fig. 1) a light emitting device 12 (the quantum wells 20 are the light emitters as in paragraph 0035) with the n-type cladding layer 18 continuing between adjacent light emitting elements (the light emitting element 20 is broken up by vias 24; the n-type cladding layer is only partially impacted by the vias so it continues between adjacent light emitting elements 20 as seen in Fig. 1).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the n-type cladding layer continue between adjacent light-emitting elements in the combination of Nakamura, Yoshino, and Matsumura as per Stokes, the motivation being that a continuous n-type layer will allow for better electron flow to the quantum wells, improving efficiency of the light emitting device (see Fig. 2 and paragraph 0041 for example).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2015/0168303 to Trupke et al. discloses a method for inspecting semiconductor wafers involving detection of photoluminescence (see claim 1 for instance); and US 2022/0399320 to Ikeda discloses a display device featuring an inspection device that inspects the emission wavelength of light emitting elements using photoluminescence or electroluminescence (see paragraph 0104).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michael A. Lyons whose telephone number is (571)272-2420. The examiner can normally be reached Monday - Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michelle Iacoletti can be reached at 571-270-5789. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Michael A Lyons/Primary Examiner, Art Unit 2877 August 19, 2026
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