DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim 5-7, 13-14 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 8-11, 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shao et al. (PGPUB 20190332738), hereinafter Shao.
Regarding claim 1, Shao teaches a method comprising:
generating, using an integrated circuit (IC) design application executing in a processor, a front end of line (FEOL) memory cell design (Fig 4, step 104), wherein the FEOL memory cell design is for a multiport memory cell ([0112] SRAM, it is well known in the art SRAM is a multiple port memory);
designing, using the IC design application, metal routing layers in a back end of line (BEOL) design (Fig. 4, step 108/110/112/114);
determining, using the IC design application, resistive-capacitive (RC) characteristics between the metal routing layers (Fig 4, step 116, at least [0024]); and
upon determining the RC characteristics and the FEOL memory cell design are unbalanced (Fig 4, step 116 “NO”), adjusting at least one of the metal routing layers in the BEOL design or dimensions of the FEOL memory cell design (Fig 4, looping back to 106, 108-114; 106 “Placing cell”, 104 “Lib cell design” is an input of 106, and [0050] “each distinct cell in a library… have unique geometry of active, gate”; 108-114 metal routings).
Regarding claim 2, Shao teaches fabricating an IC based on the metal routing layers in the BEOL design and the FEOL memory cell design ([0021]).
Regarding claim 3, Shao teaches linking the metal routing layers in the BEOL design to the FEOL memory cell design to make the multiport memory cell modular (Fig 4).
Regarding claim 8, Shao teaches the RC characteristics and the FEOL memory cell design are balanced when the RC characteristics of the metal routing layers in the BEOL satisfy a performance threshold with current dimensions of the FEOL memory cell design (Fig 4).
Regarding claim 9, Shao teaches a system (Fig 8), comprising: one or more processors; and memory storing one or more applications which, when executed by the one or more processors, perform operations comprising:
generating, using an integrated circuit (IC) design application executing in a processor (Fig 8), a front end of line (FEOL) memory cell design, wherein the FEOL memory cell design is for a multiport memory cell ([0112] argument used in rejection of claim 1 applies);
designing, using the IC design application, metal routing layers in a back end of line (BEOL) design (Fig. 4, step 108/110/112/114);
determining, using the IC design application, resistive-capacitive (RC) characteristics between the metal routing layers (Fig 4, step 116, at least [0024]); and
upon determining the RC characteristics and the FEOL memory cell design are unbalanced, adjusting at least one of the metal routing layer or dimensions of the FEOL memory cell design (Fig 4, looping back to 106, 108-114; 106 “Placing cell”, 104 “Lib cell design” is an input of 106, and [0050] “each distinct cell in a library… have unique geometry of active, gate”; 108-114 metal routings).
Regarding claim 10/17, argument used in rejection of claim 2 applies.
Regarding claim 11, argument used in rejection of claim 3 applies.
Regarding claim 15, argument used in rejection of claim 8 applies.
Regarding claim 16, Shao teaches a computer program product comprising:
one or more computer readable storage media (Fig 8); and
program instructions stored on the one or more computer readable storage media to perform operations comprising:
generating, using an integrated circuit (IC) design application executing in a processor, a front end of line (FEOL) memory cell design, wherein the FEOL memory cell design is for a multiport memory cell ([0112] argument used in rejection of claim 1 applies);
designing, using the IC design application, metal routing layers in a back end of line (BEOL) design (Fig 4, step 108/110/112/114);
determining, using the IC design application, resistive-capacitive (RC) characteristics between the metal routing layers (Fig 4, step 116, at least [0024]); and
upon determining the RC characteristics and the FEOL memory cell design are unbalanced, adjusting at least one of the metal routing layer or dimensions of the FEOL memory cell design (Fig 4, looping back to 106, 108-114; 106 “Placing cell”, 104 “Lib cell design” is an input of 106, and [0050] “each distinct cell in a library… have unique geometry of active, gate”; 108-114 metal routings).
Claim(s) 4, 12, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shao, in view of Sinha et al. (PGPUB 20120163110), hereinafter as Sinha.
Regarding claim 4, Shao teaches a method as in rejection of claim 1,
But not expressly layout of the circuit,
Sinha teaches placing a latch in a doped well in a cell for the FEOL memory cell design, wherein the doped well (the examiner is taking note that it is well known that a doped well is used for a latch) is doped oppositely than a substrate of an IC to be fabricated based on the FEOL memory cell design; and placing an inverter in a same circuit row of the cell as the latch (Fig 3A).
Since Sinha and Shao are both from the same field of semiconductor memory device, the purpose disclosed by Sinha would have been recognized in the pertinent art of Shao.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to use the layout as in Sinha into the device Shao for the purpose of enabling a layout of the memory device.
Regarding claim 12/18, argument used in rejection of claim 4 applies.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIN HUANG whose telephone number is (571)270-5798. The examiner can normally be reached M-F 9-6.
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/MIN HUANG/Primary Examiner, Art Unit 2827
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