DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim 5-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 9-10, 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho et al. (PGPUB 20190348140), hereinafter as Cho.
Regarding claim 1, Cho teaches a storage device, comprising: a memory including a memory cell array including a plurality of word lines and a plurality of bit lines, a first decoder (Fig 3, RowDecoder 261) selecting an operation word line from among the plurality of word lines, and a second decoder (Fig 3, ColDecoder 271) selecting an operation bit line from among the plurality of bit lines; and
a controller (Fig 3, circuit 201) transmitting a first address bit (Fig 3, RADDR) and a second address bit (Fig 3, CADDR), a first portion of the first address bit indicating the operation word line for selection([0049]), and a second portion of the first address bit (Fig 3, RBIN, and [0055]) and the second address bit (Fig 3, CADDR) indicating the operation bit line for selection ([0149-0150]).
Regarding claim 9, Cho teaches the plurality of bit lines are divided into two or more bit line groups, and wherein the second portion of the first address bit indicates one of the two or more bit line groups (Fig 3, and [0055]).
Regarding claim 10, Cho teaches the memory cell array is divided into two or more sub pages, and wherein the second portion of the first address bit indicates one of the two or more sub pages (Fig 3, and [0055]).
Regarding claim 13, Cho teaches a memory device, comprising: a plurality of first driving lines arranged in a first direction (Fig 3);
a plurality of second driving lines arranged in a second direction crossing the first direction (Fig 3);
a first decoder (Fig 3, 261) selecting a first driving line operating from among the plurality of first driving lines based on a first portion of a first address bit ([0049]); and
a second decoder (Fig 3, 271) selecting a second driving line operating from among the plurality of second driving lines based on a second portion of the first address bit and a second address bit ([0055], [0149-0150]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho, in view of Hinkle et al. (PGPUB 20230099478), hereinafter as Hinkle.
Regarding claim 2, Cho teaches a device as in rejection of claim 1,
But not expressly an address buffer,
Hinkle teaches a column address buffer to which the second portion of the first address bit and the second address bit are latched (Fig 1, buffer 15).
Since Hinkle and Cho are both from the same field of semiconductor memory device, the purpose disclosed by Hinkle would have been recognized in the pertinent art of Cho.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to use buffer as in Hinkle into the device of Cho for the purpose of temporarily storing address bits.
Regarding claim 14, argument used in rejection of claim 2 applies.
Claim(s) 3-4, 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho and Hinkle, in view of Ong (PGPUB 20130212431), hereinafter as Ong.
Regarding claim 3, Cho and Hinkle teaches a device as in rejection of claim 2,
But not expressly an address muxer,
Ong teaches an address multiplexer (Fig 6A, pre-decoder 134) latching the second portion of the first address bit to the column address buffer or the second decoder.
Since Ong and Cho are both from the same field of semiconductor memory device, the purpose disclosed by Ong would have been recognized in the pertinent art of Cho.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to use a pre-decoder as in Ong into the device of Cho for the purpose of directing address bit to targeted decoder.
Regarding claim 4, Hinkle teaches the address multiplexer latches the first portion of the first address bit to a row address buffer or the first decoder (Fig 1).
Regarding claim 15, argument used in rejection of claim 3 applies.
Regarding claim 16, arguments used in rejection of claim 3 and 4 apply.
Claim(s) 11-12, 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho.
Regarding claim 11, Cho teaches a device as in rejection of claim 1 with but not the timing difference wherein the second portion of the first address bit is transmitted in a first period, and the second address bit is transmitted in a second period different from the first period. It would have been obvious to one of ordinary skill in the art at the time the invention was made to arrange two porting of bits transferring in two different stages, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding claim 12/17, argument used in rejection of claim 11 applies.
Regarding claim 18, Cho teaches a controller, comprising:
an address bit generator (Fig 3, 261/201) generating a first bit indicating an operation word line among a plurality of word lines (Fig 3, WLs), a second bit (Fig 3, RBIN, and [0055]) indicating one among a plurality of sub pages (Fig 3, different groups MB1…K), and a third bit (CADDR) indicating an operation bit line among a plurality of bit lines included in a sub page indicated by the second bit; and
an address bit transmitter transmitting the first bit and the second bit in a first period and transmitting the third bit in a second period (case law used in rejection of claim 11 applies).
Regarding claim 19/20, argument used in rejection of claim 11 applies.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIN HUANG whose telephone number is (571)270-5798. The examiner can normally be reached M-F 9-6.
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/MIN HUANG/ Primary Examiner, Art Unit 2827
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