DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 08/19/2026 have been fully considered but they are not persuasive. Applicant argues that the combination of Levy and Abu-Nada fails to teach or suggest:
“the quantum error correction circuit is configured to periodically perform a quantum error correction code on the plurality of memory qubits with a time period based on a ratio of the error correction error rate and the idle error rate.”
The Examiner respectfully disagrees.
Applicant first argues that Levy merely concerns scheduling gate operations within an error-correction operation to minimize idle time and therefore does not teach determining the period between successive quantum error correction operations. The Examiner agrees that Levy alone is not relied upon for determining the claimed QEC periodicity. Rather, Levy is relied upon for its teachings concerning a quantum-memory architecture having distinct error behavior during idle/storage operations and during active gate/error-correction operations.
In particular, Levy, Section 3 (“Physical Qubit, Native Gate Set, and Noise Assumptions for Logical Qubit”), expressly distinguishes memory or idle operation from active quantum-gate operation. Levy’s Table 1 assigns the memory operation I a failure probability of 5\times 10^{-7}, while active operations such as X, X_{\pi/2}, and CPHASE are assigned substantially larger failure probabilities, including approximately 1.2\times 10^{-2}. Levy further states that an idle interval can comprise an arbitrary number of memory gates and discusses use of dynamical decoupling to reduce memory-error probability. Thus, Levy provides the claimed concept of memory qubits having an associated idle or memory error rate, with that rate being lower than error rates associated with active qubit operations. Applicant’s argument regarding Levy therefore does not address the full rejection because the rejection relies on Abu-Nada for determining how often QEC should be performed.
Furthermore, Abu-Nada, Section I and Section II (“Derivation of the Mathematical Formula for P_L”), directly addresses the frequency at which quantum error correction should be applied.
Abu-Nada explains that QEC need not be performed after every logical operation because the QEC process itself may introduce errors. Instead, QEC may be performed after a selected number of intervening operations.
More specifically, Abu-Nada defines:
N logical operations;
m operations between successive QEC operations;
N/m blocks; and
the logical error rate P_L as a function of m,
and then determines the value of m that minimizes the logical error rate. Accordingly, Abu-Nada teaches selecting the spacing or frequency of periodic QEC operations based on error considerations.
Applicant argues that \epsilon_g in Abu-Nada is merely a gate-error probability and therefore cannot correspond to an idle-error rate. That argument is not persuasive because it overlooks Abu-Nada’s actual implementation. In Abu-Nada, Section III (“Monte Carlo Simulation of P_L”), the authors state that the m intervening logical operations between QEC cycles are:
“simply wait operations which in the absence of errors do not change the qubits’ state.” Thus, in the implementation used to evaluate the optimal QEC frequency, the operations occurring between QEC cycles are not necessarily computational transformations; they are expressly modeled as waiting operations. Further, in Abu-Nada, Section II.A (“Logical gate and QEC model”), Abu-Nada states that errors from movement or hold operations are not modeled as a separate category but “may [be] incorporated into the above categories if desired.” Therefore, Applicant’s assertion that Abu-Nada’s model excludes idle or hold error is inconsistent with Abu-Nada’s express disclosure.
Applicant next argues that Abu-Nada’s QEC error terms \epsilon_s,\epsilon_o,\epsilon_c,\epsilon_d are functions of the physical gate error \epsilon_g, and therefore do not represent an “error correction error rate.” This argument is not persuasive because claim 35 does not require the error-correction error rate to be physically or statistically independent from an underlying gate-error probability.
In Abu-Nada, Section II.A, Abu-Nada expressly separates errors associated with the QEC procedure from those associated with the intervening operations.
For example, Abu-Nada defines:
correction errors \epsilon_c, caused by physical gates directly applied to data as part of QEC;
syndrome errors \epsilon_s;
omission errors \epsilon_o; and
double errors \epsilon_d.
Abu-Nada therefore expressly identifies error probabilities attributable to performance of the QEC operation itself. The fact that these QEC-error probabilities may ultimately be functions of an underlying physical gate-error parameter does not negate their character as errors associated with the QEC operation. Claim 35 does not recite that the “error correction error rate” must originate from an error mechanism completely independent of the mechanism underlying the idle error rate.
Applicant particularly argues that Abu-Nada’s quantity d/c_1 does not constitute the claimed “ratio of the error correction error rate and the idle error rate.” The Examiner does not interpret claim 35 as requiring that the prior art expressly disclose a simple two-variable formula of the form:
T=\frac{E_{\text{QEC}}}{E_{\text{idle}}}.
Claim 35 recites only that the time period is “based on a ratio” of the respective error rates.
In Abu-Nada, Section II.C (“Minimizing P_L(m)”), the optimum value of m is determined from d/c_1. Abu-Nada states that the dependence of P_L on m is determined by that quantity. The numerator of d/c_1 contains QEC-related error quantities \epsilon_c,\epsilon_s,\epsilon_o,\epsilon_d, while the denominator contains \epsilon_g^2, representing the error contribution associated with the intervening operations. Read together with Abu-Nada’s disclosure that those intervening operations may be wait operations, the reference teaches choosing QEC frequency from a mathematical relationship that compares the error introduced by QEC against the error accumulated during the operations between QEC cycles. That is the relevant teaching relied upon in the obviousness combination.
Applicant further argues that Abu-Nada selects a number m of operations, rather than a “time period.” That distinction is not persuasive when Abu-Nada is considered in combination with Levy. Levy, Section 3, expressly uses a fixed 30-ns clock period. Levy also defines an idle period as an arbitrary number N of 30-ns memory operations. Accordingly, when Abu-Nada’s selected number m of intervening wait/memory operations is implemented in Levy’s fixed-duration architecture, m directly determines an elapsed time:
T=m\tau,
where \tau is the duration of the individual memory/wait operation.
Therefore, one of ordinary skill would have understood that selecting the number of wait operations between QEC cycles equivalently determines the time period between QEC cycles.
Thus, Abu-Nada teaches that performing QEC too frequently can increase total error because QEC itself introduces error, and therefore the frequency should be optimized. And Levy teaches that idle/memory errors and active-gate/QEC errors differ substantially and expressly observes that errors occurring in syndrome-extraction gates can contribute more significantly than data errors occurring during idle periods.
Thus, one of ordinary skill in the art would have had reason to apply Abu-Nada’s QEC-frequency optimization to Levy’s quantum-memory architecture so as to balance:
errors accumulated during memory/idling, against
errors introduced by performing the QEC operation,
thereby reducing overall logical error while avoiding unnecessarily frequent QEC.
Thus, Applicant’s arguments are not persuasive because they are directed to limitations not presently recited in claim 35. In particular, claim 35 does not require that the idle error rate and error correction error rate be independently measured or originate from physically independent error mechanisms, nor does the claim require the time period to equal a simple quotient of two expressly labeled error-rate variables. Abu-Nada teaches selecting the frequency of QEC based on the relative error contributions of the noisy QEC operation and the intervening operations, which Abu-Nada expressly implements as wait operations, while Levy expressly teaches a quantum-memory architecture having a low memory/idle error rate relative to active gate-operation errors and fixed-duration memory operations. See Abu-Nada, Sections II.A, II.C, and III; Levy, Sections 3, 6, and 7. One of ordinary skill in the art therefore would have found it obvious to determine the periodic QEC interval in Levy’s quantum-memory architecture using Abu-Nada’s error-based frequency optimization. If Applicant intends to distinguish the prior art by requiring a more specific mathematical relationship between independently defined idle and error-correction error rates, such distinction must be positively recited in the claim rather than supplied through attorney argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 35-48 are rejected under 35 U.S.C. 103 as being unpatentable over Levy et al. “The impact of classical electronics constraints on a solid-state logical qubit memory” (hereinafter Levy) and further in view of Abu-Nada et al. “Optimizing the Frequency of Quantum Error Correction using the [[7,1,3]] Steane Code” (hereinafter Abu-Nada).
Claim 35: Levy teaches a resource-efficient quantum error correction assembly comprising:
a quantum memory comprising a plurality of memory qubits having an associated idle error rate (e.g. Section 2: “A key concept… is the redundant encoding of a logical qubit in the state of many physical qubits.” Page 14: “Holding qubits in memory contributes to qubit errors.” And Sec. 3: “Qubits also experience the ‘identity gate’ by sitting idle.” Table 1: idle gate I^* has error probability 1\times10^{-2}; memory qubits are the data qubits in Fig. 2, BS9 code); and
a quantum error correction circuit comprising a plurality of gate qubits having an associated error correction error rate (e.g. Section 2: “Every quantum computation can be expressed as a quantum circuit in which a sequence of elementary transformations called gates act on a collection of… qubits.” And Sec. 5, Fig. 3 (ancilla qubits); Table 1 gives error rates for X_{\pi/2}, CPHASE, etc., used in QEC), the idle error rate being less than the error correction error rate (e.g. Table 1: bare idle I^* error = 1\times10^{-2}; but with dynamical decoupling, the improved idle I error = 5\times10^{-7}, which is lower than, e.g., X_{\pi/2} error = 1.2\times10^{-2}. The specification explicitly contemplates regimes where idle errors are smaller, after DD).
Levy fails to teach that the quantum error correction circuit is configured to periodically perform a quantum error correction code on the plurality of memory qubits with a time period based on a ratio of the error correction error rate and the idle error rate. However, Levy explains, in Page 14, that the architecture requires scheduling of error correction operations and optimization of schedules to minimize idle errors (e.g. “We wish to schedule all the circuits… to minimize the total idle time of all qubits.” Furthermore, in Abu-Nada, Eq. (7)–(12): P_L \approx d/m + c_0 + c_1 m, and m_{min} is a function of \frac{d}{c_1}, which itself is a ratio of QEC error terms to \epsilon_g^2 (gate error, analogous to idle error). This is exactly “a time period based on a ratio of the error correction error rate and the idle error rate.” Therefore, a POSITA, before the effective filing date of the claimed invention, would have combined Levy’s hardware-specific error rates (Table 1) with Abu-Nada’s optimization method to determine the optimal QEC period. The period necessarily depends on the ratio of QEC-induced error to idle error; this is a direct application of Abu-Nada’s teaching to Levy’s architecture.
Claim 36: Levy and Abu-Nada teach the resource-efficient quantum error correction assembly of claim 35, wherein quantum error correcting operations comprise a surface code. For instance, Levy teaches, in Sec. 4, that “surface codes [16]” as one of three local check codes.
Claim 37: Levy and Abu-Nada teach the resource-efficient quantum error correction assembly of claim 35, wherein quantum error correcting operations comprise a surface code having a code distance and the time period is based on a time when the numbers of idle errors is comparable to the code distance. For instance, Levy discusses code distance implicitly (BS9 is distance-3) and threshold calculations (e.g., Sec. 7).
Claim 38: Levy and Abu-Nada teach the resource-efficient quantum error correction assembly of claim 35, but fail to teach that the quantum error correcting code is a Gottesman-Kitaev-Preskill (GKP) code. However, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to use any known quantum error correction code in the teaching of Levy and Abu-Nada, since such a modification would have the simple substitution of known technique for another (e.g. predictable design choices).
Claim 39: Levy and Abu-Nada teach the resource-efficient quantum error correction assembly of claim 35, but fail to teach that the quantum error correcting code is a bosonic mode code. However, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to use any known quantum error correction code in the teaching of Levy and Abu-Nada, since such a modification would have the simple substitution of known technique for another (e.g. predictable design choices).
Claim 40: Levy and Abu-Nada teach the resource-efficient quantum error correction assembly of claim 35, but fail to teach that the quantum error correcting code is a biased error quantum error correction code. However, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to use any known quantum error correction code in the teaching of Levy and Abu-Nada, since such a modification would have the simple substitution of known technique for another (e.g. predictable design choices).
Claim 41: Levy and Abu-Nada teach the resource-efficient quantum error correction assembly of claim 35, wherein: the plurality of memory qubits is a first logical qubit; the error correction circuit is associated with a plurality of logical qubits including the first logical qubit; and each logical qubit of the plurality of logical qubits has error correction code performed thereon periodically by the error correction code. For instance, in Levy, Fig. 3 shows an “enclosed architecture” with many qubits and Sec. 5 discusses routing and scalability.
Claim 42: Levy and Abu-Nada teach the resource-efficient quantum error correction assembly of claim 41, wherein the error correction circuit performs the error correction code sequentially on each of the logical qubits. For instance, Levy’s scheduling (Sec. 6) and routing constraints (Table 2) strongly suggest sequential rather than fully parallel QEC.
Claim 43: Levy and Abu-Nada teach the resource-efficient quantum error correction assembly of claim 41, wherein the number of memory qubits in each logical qubit is based on the code distance, the idle error rate and the error correction error rate. For instance, Levy’s threshold analysis (Table 5) ties code distance (hence number of qubits) to physical error rates
Claim 44: Levy and Abu-Nada teach the resource-efficient quantum error correction assembly of claim 35wherein the plurality of gate qubits of the error correction circuit is further configured to perform logical operations. For instance, Levy, in Sec. 2, discusses Clifford gates (CNOT, H, etc.) for computation, not just correction.
Claim 45: Levy and Abu-Nada teach the resource-efficient quantum error correction assembly of claim 442wherein the logical operations are fault-tolerant logical operations. For instance, Levy, in Sec. 4, discusses fault-tolerant syndrome extraction (“repeat twice”).
Claim 46: Levy and Abu-Nada teach the resource-efficient quantum error correction assembly of claim 35, but fail to teach that the quantum memory is a random access quantum memory. However, Levy teaches a quantum memory formed from Si DQD qubits arranged in a grid (Fig. 3). The architecture includes addressable control lines (Sec. 5, Fig. 5) and multiplexing/demultiplexing circuits. Such addressing inherently provides the ability to access individual qubits or groups of qubits, i.e., random access. Therefore, a POSITA would recognize that any large-scale quantum memory must support random access to be useful. Levy’s use of MUX/DEMUX (Fig. 5) and the enclosed architecture (Fig. 3) with multiple control lines directly teaches the ability to select individual qubits for read/write operations. Calling this “random access” is merely a recitation of the inherent property of the disclosed memory. Alternatively, RAQM was a well-known concept in the art (e.g., using quantum buses or addressing schemes). Implementing the obvious QEC assembly of claim 35 as a random access quantum memory would have been a predictable variation.
Claim 47: Levy and Abu-Nada teach the resource-efficient quantum error correction assembly of claim 35, but fail to teach that the quantum memory comprises a superconducting three-dimensional cavity having a plurality of modes. However, superconducting 3D cavities were a well-known platform for quantum memory (e.g., “3D transmon” and “cavity QED” systems). Therefore, a POSITA seeking to build the QEC assembly of claim 35 would have been motivated to select a superconducting cavity because of its long coherence times and high-Q modes – features that directly reduce the idle error rate, which is a key parameter in the QEC period optimization of claim 35. Substituting a known alternative quantum memory (superconducting cavity) for Levy’s Si DQD memory is a simple substitution of one known element for another that yields predictable results (low idle errors, high fidelity).
Claim 48: Levy and Abu-Nada teach the resource-efficient quantum error correction assembly of claim 35, but fail to teach that the quantum memory comprises a plurality of electron spin states nuclear spin states. However, Levy, Sec. 3, teaches that “The physical qubit for this logical qubit analysis is a two electron spin system.” The qubit states are singlet/triplet – i.e., electron spin states. Therefore, a POSITA would have found it obvious to substitute nuclear spins for electron spins because both are spin-based qubits with analogous control mechanisms, and such substitution would not change the claimed QEC period optimization.
Claim(s) 49 is rejected under 35 U.S.C. 103 as being unpatentable over Levy and Abu-Nada as applied to claim 35 above, and further in view of LaHaye et al., “Nanomechanical measurements of a superconducting qubit”.
Claim 49: Levy and Abu-Nada teach the resource-efficient quantum error correction assembly of claim 35, but fail to teach that the quantum memory comprises a nanomechanical resonator having a plurality of modes. However, nanomechanical resonators (e.g., NEMS-based qubits or resonators) were a known alternative quantum memory platform (see LaHaye et al, Abstract). A POSITA would have recognized that a nanomechanical resonator can store quantum information in its vibrational modes, and that such a memory can be integrated into the QEC assembly of claim 35. The selection of a resonator over spin qubits is a predictable design choice driven by factors such as coupling strength, decoherence rates, and ease of fabrication. The claimed limitation adds no unexpected functionality to the base QEC assembly.
Claim(s) 50 is rejected under 35 U.S.C. 103 as being unpatentable over Levy and Abu-Nada as applied to claim 35 above, and further in view of Koch et al, “Charge insensitive qubit design derived from the Cooper pair box”.
Claim 50: Levy and Abu-Nada teach the resource-efficient quantum error correction assembly of claim 35, but fail to teach that the plurality of gate qubits comprises a plurality of transmon qubits. However, transmon qubits were, at the time of the invention, a dominant and conventional implementation of superconducting qubits for gate operations (see Koch et al, Abstract). Therefore, a POSITA designing the QEC assembly of claim 35 would have been motivated to use transmons for the gate qubits because transmons have high coherence, well-developed two-qubit gates (e.g., CPHASE), and are compatible with standard microwave control – all features that directly reduce the “error correction error rate” recited in claim 35. Substituting transmons for Levy’s Si DQD gate qubits is a simple substitution of a known equivalent performing the same function (fault-tolerant quantum gates) with predictable results.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 9/3/2026
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