DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on January 9, 2025 has been considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-6, 9-15, and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 10,892,015 B2 to Kang-Bin Lee, et al. (hereafter Lee) in view of US 8,045,384 B2 to Yingda Dong, et al. (hereafter Dong).
Regarding Independent Claim 1, Lee discloses a memory device, comprising:
a memory cell array (A memory cell array: Lee, col.3:65-4:2); and
a peripheral circuit coupled to the memory cell array and configured to perform operations comprising (A control circuit: Lee, col.2:43-44):
during a program operation (Disclosing a programming operation: Lee, col.3:62-64) of a first memory cell in the memory cell array (The operation taking place on a first memory cell: Lee, col.2:8-9):
applying a first voltage to a first line coupled to the first memory cell during a first time period (Applying a first voltage VPC1: Lee, col.17:64),
wherein the first line comprises one of a source line and a bit line coupled to the first memory cell (VPC1 being applied to source line: Lee, col.17:65);
applying a first programming voltage to a first word line coupled to the first memory cell during a second time period after the first time period (VPC1 applied in preparation for the first program loops: Lee, col.17:65-66);
applying a second voltage to the first line during a third time period after the second time period (Applying a second voltage during later program loops: Lee, col.17:67),
wherein the second voltage is higher than the first voltage (Second voltage VPC2 being higher than VPC1: Lee, col.17:66-67); and
applying a second programming voltage to the first word line during a fourth time period after the third time period (VPC2 being applied in preparation for the later program loops: Lee, col.18:1-2).
Lee teaches increasing the source/bit line voltage helps boost the channel voltage, but fails to disclose the later programming pulse durations being shorter than the earlier programming pulse durations. Dong, however, discloses a programming operation wherein the fourth time period is shorter than the second time period (Using shorter duration programming pulses at higher pulse levels: Dong, col.3:11-14). Dong teaches using shorter duration programming pulses at higher programming voltages can help reduce program disturb (Dong, col.3:11-14). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the the short duration programming pulses of Dong with the increased channel boosting voltage of Kim, with a reasonable expectation of success. Both inventions are well known in the field of reducing program disturb effects in memory array programming operations and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 2 and the substantially similar limitations of Claims 11 and 20, Lee discloses the memory device according to claim 1, wherein
memory cells in the memory cell array are programmed in a direction from memory cells closest to bit lines of the memory cell array to memory cells closest to the source line (Recommending programming memory cells in a Top to Bottom [T2B] order: Lee, col.13:66-67; See also, Figure 13 showing the Top line being the bitline and the bottom line being the source line: Lee, Figure 13).
Regarding Claim 3 and the substantially similar limitations of Claim 12, Lee discloses the memory device according to claim 1, wherein
the second programming voltage is higher than the first programming voltage (The second programming voltage VPGM2 being higher than the first programming voltage VPGM1: Lee, Figure 9).
Regarding Claim 4 and the substantially similar limitations of Claim 13, Lee discloses the memory device according to claim 1, wherein the operations further comprise:
applying, during the first time period (T1: Lee, Figure 17) and the second time period (T4: Lee, Figure 17),
a third voltage and a fourth voltage respectively to a select line coupled to a select gate transistor in the memory cell array (Third voltage VSON1 and second voltage VSON2 being applied to SSLs: Lee, Figure 17),
wherein the third voltage is higher than the fourth voltage (Wherein VSON1 is higher than VSON2: Lee, Figure 17).
Regarding Claim 5 and the substantially similar limitations of Claim 14, Lee discloses the memory device according to claim 1, wherein the operations further comprise:
applying a fifth voltage to the first word line during the first time period (Applying voltage VRD to the select wordline during the first time period: Lee, Figure 17),
wherein the fifth voltage is lower than the first programming voltage (Wherein VRD is less than the first programming voltage VPGM: Lee, Figure 17).
Regarding Claim 6 and the substantially similar limitations of Claim 15, Lee discloses the memory device according to claim 1, wherein the operations further comprise:
applying a sixth voltage to a second word line during the first time period (Applying voltage VPASS1 to the second wordline during the first time period: Lee, Figure 17),
wherein the sixth voltage is lower than the first programming voltage (Wherein VPASS1 is less than VPGM: Lee, Figure 17); and
applying a seventh voltage to the second word line during the second time period (Applying VPASS2 to the second wordline: Lee, Figure 17),
wherein the seventh voltage is higher than the sixth voltage (Wherein VPASS2 is higher than VPASS1: Lee, Figure 17).
Regarding Claim 9 and the substantially similar limitations of Claim 18, Lee discloses the memory device according to claim 1, wherein
the memory device is a NAND memory device (Disclosing a NAND memory device: Lee, col.4:2-5).
Regarding Independent Claim 10, Lee discloses a method, comprising:
applying a first voltage to a first line coupled to a first memory cell in a memory cell array (The operation taking place on a first memory cell: Lee, col.2:8-9) of a memory device during a first time period (Applying a first voltage VPC1: Lee, col.17:64), wherein the first line comprises one of a source line and a bit line coupled to the first memory cell (VPC1 being applied to source line: Lee, col.17:65);
applying a first programming voltage to a first word line coupled to the first memory cell during a second time period after the first time period (A first programming voltage applied to the memory cells during a second time period after the first period: Lee, Figure 17);
applying a second voltage to the first line during a third time period after the second time period (Applying a second voltage during later program loops: Lee, col.17:67), wherein the second voltage is higher than the first voltage (Second voltage VPC2 being higher than VPC1: Lee, col.17:66-67); and
applying a second programming voltage to the first word line during a fourth time period after the third time period (A second programming voltage applied to the memory cells during a second time period after the first period: Lee, Figure 17).
Lee teaches increasing the source/bit line voltage helps boost the channel voltage, but fails to disclose the later programming pulse durations being shorter than the earlier programming pulse durations. Dong, however, discloses a programming operation wherein the fourth time period is shorter than the second time period (Using shorter duration programming pulses at higher pulse levels: Dong, col.3:11-14). Dong teaches using shorter duration programming pulses at higher programming voltages can help reduce program disturb (Dong, col.3:11-14). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the the short duration programming pulses of Dong with the increased channel boosting voltage of Kim, with a reasonable expectation of success. Both inventions are well known in the field of reducing program disturb effects in memory array programming operations and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Independent Claim 19, Lee discloses a memory system, comprising:
a memory device, comprising (A memory device: Lee, col.4:2-5):
a memory cell array (A memory cell array: Lee, col.3:65-4:2); and
a peripheral circuit coupled to the memory cell array (A control circuit: Lee, col.2:43-44) and configured to perform operations comprising:
during a program operation (Disclosing a programming operation: Lee, col.3:62-64) of a first memory cell in the memory cell array (The operation taking place on a first memory cell: Lee, col.2:8-9):
applying a first voltage to a first line coupled to the first memory cell during a first time period (Applying a first voltage VPC1: Lee, col.17:64),
wherein the first line comprises one of a source line and a bit line coupled to the first memory cell (VPC1 being applied to source line: Lee, col.17:65);
applying a first programming voltage to a first word line coupled to the first memory cell during a second time period after the first time period (VPC1 applied in preparation for the first program loops: Lee, col.17:65-66);
applying a second voltage to the first line during a third time period after the second time period (Applying a second voltage during later program loops: Lee, col.17:67),
wherein the second voltage is higher than the first voltage (Second voltage VPC2 being higher than VPC1: Lee, col.17:66-67); and
applying a second programming voltage to the first word line during a fourth time period after the third time period (VPC2 being applied in preparation for the later program loops: Lee, col.18:1-2), and
a controller coupled to the memory device and configured to send one or more signals to the memory device to initiate the operations (A circuit connected to a memory array and configured to initiate programming operations is inherent in any functional memory array).
Lee teaches increasing the source/bit line voltage helps boost the channel voltage, but fails to disclose the later programming pulse durations being shorter than the earlier programming pulse durations. Dong, however, discloses a programming operation wherein the fourth time period is shorter than the second time period (Using shorter duration programming pulses at higher pulse levels: Dong, col.3:11-14). Dong teaches using shorter duration programming pulses at higher programming voltages can help reduce program disturb (Dong, col.3:11-14). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the the short duration programming pulses of Dong with the increased channel boosting voltage of Kim, with a reasonable expectation of success. Both inventions are well known in the field of reducing program disturb effects in memory array programming operations and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 7 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 10,892,015 B2 to Kang-Bin Lee, et al. (hereafter Lee) and US 8,045,384 B2 to Yingda Dong, et al. (hereafter Dong) in view of US 8,116,140 B2 to Yingda Dong, et al. (hereafter Dong ‘140).
Regarding Claim 7 and the substantially similar limitations of Claim 16, Lee discloses the memory device according to claim 1, wherein the operations further comprise:
applying an eighth voltage to the first line during a fifth time period after the fourth time period, wherein the eighth voltage is higher than the second voltage (Disclosing continually increasing the voltage applied to the first line in preparation for each successive programming pulse: Lee, col.17:60-63); and
applying a third programming voltage to the first word line during a sixth time period after the fifth time period (Applying a successively higher voltage programming pulse to the wordline: Dong, Figure 13),
wherein the third programming voltage is higher than the second programming voltage (Applying a successively higher voltage programming pulse to the wordline: Dong, Figure 13).
Lee and Dong disclose increasing the voltage of successive programming pulses and increasing the source line voltage to increase channel boosting as the programming voltage increases. Dong further discloses reducing the programming pulse duration at a certain point, but fails to disclose further decreasing the programming pulse duration as programming pulse voltage continues to increase. Dong ‘140, however, discloses a programming pulse operation wherein the sixth time period is shorter than the fifth time period (Each successive set of programming pulses being of a shorter duration: Dong ‘140, Figure 9A). Dong ‘140 teaches successively decreasing the overall duration of the programming pulse at higher voltages helps minimize program disturb, which is more of a problem at higher programming voltages (Dong ‘140: col.10:52-67). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the successively shorter duration pulse widths of Dong ‘140 with the pulse duration width decrease of Dong and the increasing channel boosting of Lee, with a reasonable expectation of success. All inventions are well known in the field of reducing program disturb effects in memory array programming operations and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 8 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 10,892,015 B2 to Kang-Bin Lee, et al. (hereafter Lee) and US 8,045,384 B2 to Yingda Dong, et al. (hereafter Dong) in view of US 2009/0161437 A1 to Hong-Beom Pyeon, et al. (hereafter Pyeon).
Regarding Claim 8 and the substantially similar limitations of Claim 17, Lee discloses the memory device according to claim 1, but fails to disclose the further limitations of Claim 8. Pyeon, however, discloses a memory device as in Claim 1, wherein the operations further comprise:
applying a ninth voltage to the first line during the second time period, wherein the ninth voltage is higher than the first voltage (Showing a high voltage V4 applied to the selected source line CSL during the program pulse phase: Pyeon, Figure 10).
Pyeon teaches the high voltage on the select line reduces power consumption (Pyeon, ¶[0062]) while minimizing program disturb associated with unboosted configurations (Pyeon, ¶[0006]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the source line boosting technique of Pyeon with the increased channel boosting method of Kim, with a reasonable expectation of success. Both inventions are well known in the field of reducing program disturb effects in programming operations of a memory array through selective channel boosting and the combination of known inventions with predictable results is obvious and not patentable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 7,324,383 B2 to Michele Incarnati, et al.: Disclosing a ISPP process wherein the source line voltage is increased during the programming pulse phase.
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/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824
/DOUGLAS KING/Primary Examiner, Art Unit 2824
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