DETAILED ACTION
General Remarks
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3. When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
5. Applicants seeking an interview with the examiner, including Microsoft Team Meeting, are encouraged to fill out the online Automated Interview Request (AIR) form
(https://www.uspto.gov/sites/default/files/documents/PTOL413A.pdf). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
6. Status of claim(s) to be treated in this office action:
a. Independent: 1, 8 and 15.
b. Pending: 1-20.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 8-10, 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee PG PUB 20180158505 (hereinafter Lee).
Regarding independent claim 1, Lee teaches a memory device (figure 1) comprising:
a memory cell array including a plurality of cell strings each extending in a vertical direction on a substrate (figure 4); and
a row decoder (121 in figure 2), wherein each cell string of the plurality of cell strings comprises a plurality of memory cells (MC1-MCn in figure 5) respectively connected to a plurality of word lines (Wl1-WLn in figure 5), a ground erase control transistor (SST in figure 5) connected to a ground erase control line (SSL1-SSL2 in figure 5), and at least one dummy memory cell (SDC1 or SDC2 in figure 5) connected to a dummy word line (SDWL1 or SDWL2 in figure 5), wherein the ground erase control transistor (SST in figure 5) and the at least one dummy memory cell (SDC1/SDC2 in figure 5) are connected between a common source line (CSL in figure 5) and the plurality of memory cells (MC1-MCn in figure 5), and wherein the plurality of word lines (WL1-WLn in figure 5) comprise first word lines (e.g., WL1/WL2 in figure 5) and second word lines (e.g., WLn-2/WLn-1/WLn in figure 5), wherein the first word lines (e.g., WL1/WL2 in figure 5) are connected to memory cells that are closer to the ground erase control transistor (SST in figure 5) than are memory cells to which the second word lines (e.g., WLn-1/WLn in figure 5) are connected; and
wherein the row decoder (121 in figure 2) is configured to apply, during an erase operation (figures 6, 7, [0127]-[0131], Lee teaches that, in response to an erase command, a pre-program pulse is first applied to the wordlines of the selected memory block, followed by application of an erase-prohibition voltage to the dummy word lines while erase voltage is applied to source line (figure 6, Steps 601-605). Accordingly, Lee’s erase set up period includes the preparatory pre-program interval and subsequent interval during which the common-source erase voltage rises to its target level) on the memory cell array, (i) a first bias voltage (pre-PGM in figure 7) to the first word lines (e.g., WL1/WL2 in figure 5) and the dummy word line (SDWL1 or SDWL2 in figure 5) in a first period (t0-t1 in figure 7) of an erase setup period, and (ii) a second bias voltage (0V in figure 7), at a level lower than a level of the first bias voltage (pre-PGM in figure 7), to the first word lines (e.g., WL1/WL2 in figure 5) and the dummy word line (SDWL1 or SDWL2 in figure 5) in a second period (t1-t2 in figure 7), after the first period, of the erase setup period, wherein the erase setup period comprises a period in which a level of a voltage applied to the common source line (CSL in figure 5) increases to an erase voltage level (Verase in figure 9, [0122], “…the semiconductor memory device applies the erase voltage Verase to a common source line CSL…the semiconductor memory device may apply the erase voltage Verase to a node MTSRC coupled to the common source line CSL…”) that is a target voltage level, and wherein the second period (t1-t2 in figure 7) starts before the level of the voltage applied to the common source line reaches the erase voltage level.
Regarding claim 2, Lee teaches the memory device of claim 1, wherein a level of the first bias voltage (pre-PGM in figure 7) is higher than a level of the voltage applied to the common source line in the first period (t0-t1 in figure 7).
Regarding claim 3, Lee teaches the memory device of claim 1, wherein a number of the first word lines (e.g., WL1/WL2 in figure 5) is less than a number of the second word lines (e.g., WLn-2/WLn-1/WLn in figure 5).
Regarding independent claim 8, Lee teaches a memory system (figure 1) comprising:
a memory controller (200 in figure 1); and
a memory device (100 in figure 1) configured to perform an erase operation in response to an erase command received from the memory controller (figure 6, figure 7), wherein the memory device comprises:
a memory cell array including a plurality of cell strings each extending in a vertical direction on a substrate (figure 4), and a row decode r(121 in figure 2), wherein each cell string of the plurality of cell strings comprises:
a plurality of memory cells (MC1-MCn in figure 5) respectively connected to a plurality of word lines (Wl1-WLn in figure 5), a ground erase control transistor (SST in figure 5) connected to a ground erase control line (SSL1-SSL2 in figure 5), and at least one dummy memory cell (SDC1 or SDC2 in figure 5) connected to a dummy word line (SDWL1 or SDWL2 in figure 5), wherein the ground erase control transistor (SST in figure 5) and the at least one dummy memory cell (SDC1 or SDC2 in figure 5) are connected between a common source line (CSL in figure 5) and the plurality of memory cells (MC1-MCn in figure 5), and wherein the plurality of word lines (WL1-WLn in figure 5) comprise first word lines (e.g., WL1/WL2 in figure 5) and second word lines (e.g., WLn-2/WLn-1/WLn in figure 5), wherein the first word lines (e.g., WL1/WL2 in figure 5) are connected to memory cells that are closer to the ground erase control transistor than are memory cells to which the second word lines (e.g., WLn-2/WLn-1/WLn in figure 5) are connected; and
wherein the row decoder (121 in figure 2) is configured to apply, during an erase operation (figures 6, 7, [0127]-[0131], Lee’s erase set up period includes the preparatory pre-program interval and subsequent interval during which the common-source erase voltage rises to its target level) on the memory cell array, (i) a first bias voltage (pre-PGM in figure 7) to the first word lines (e.g., WL1/WL2 in figure 5) and the dummy word line (SDWL1 or SDWL2 in figure 5) in a first period (t0-t1 in figure 7) of an erase setup period, and (ii) a second bias voltage (0V in figure 7), at a level lower than a level of the first bias voltage (pre-PGM in figure 7), to the first word lines (e.g., WL1/WL2 in figure 5) and the dummy word line (SDWL1 or SDWL2 in figure 5) in a second period (t1-t2 in figure 7), after the first period, of the erase setup period, wherein the erase setup period comprises a period in which a level of a voltage applied to the common source line (CSL in figure 5) increases to an erase voltage level (Verase in figure 9, [0122], “…the semiconductor memory device applies the erase voltage Verase to a common source line CSL…the semiconductor memory device may apply the erase voltage Verase to a node MTSRC coupled to the common source line CSL…”) that is a target voltage level, and wherein the second period starts before the level of the voltage applied to the common source line reaches the erase voltage level.
Regarding claim 9, Lee teaches the memory system of claim 8, wherein a level of the first bias voltage (pre-PGM in figure 7) is higher than a level of the voltage applied to the common source line in the first period (t0-t1 in figure 7).
Regarding claim 10, Lee teaches the memory system of claim 8, wherein a number of the first word lines (e.g., WL1/WL2 in figure 5) is less than a number of the second word lines (e.g., WLn-2/WLn-1/WLn in figure 5).
Regarding independent claim 15, Lee teaches an erasing method for a memory device (figure 6), wherein the memory device (figure 1) comprises a memory cell array including a plurality of cell strings each extending in a vertical direction on a substrate (figure 4), wherein each cell string of the plurality of cell strings comprises a plurality of memory cells (MC1-MCn in figure 5) respectively connected to a plurality of word lines (Wl1-WLn in figure 5), a ground erase control transistor (SST in figure 5) connected to a ground erase control line (SSL1-SSL2 in figure 5), and at least one dummy memory cell (SDC1 or SDC2 in figure 5) connected to a dummy word line (SDWL1 or SDWL2 in figure 5), wherein the ground erase control transistor (SST in figure 5) and the at least one dummy memory cell (SDC1 or SDC2 in figure 5) are connected between a common source line (CSL in figure 5) and the plurality of memory cells (MC1-MCn in figure 5), and wherein the plurality of word lines (WL1-WLn in figure 5) comprise first word lines (e.g., WL1/WL2 in figure 5) and second word lines (e.g., WLn-2/WLn-1/WLn in figure 5), wherein the first word lines (e.g., WL1/WL2 in figure 5) are connected to memory cells that are closer to the ground erase control transistor (SST in figure 5) than are memory cells to which the second word lines (e.g., WLn-1/WLn in figure 5) are connected, and wherein the erasing method (figures 6, 7) comprises: applying a first bias voltage (pre-PGM in figure 7) to the first word lines (e.g., WL1/WL2 in figure 5) and the dummy word line (SDWL1 or SDWL2 in figure 5) in a first period (t0-t1 in figure 7) of an erase setup period; and applying a second bias voltage (0V in figure 7), at a level lower than a level of the first bias voltage, to the first word lines (e.g., WL1/WL2 in figure 5) and the dummy word line (SDWL1 or SDWL2 in figure 5) in a second period (t1-t2 in figure 7). after the first period, of the erase setup period, wherein the erase setup period comprises a period in which a level of a voltage applied to the common source line (CSL in figure 5) increases to an erase voltage level (Verase in figure 9, [0122], “…the semiconductor memory device applies the erase voltage Verase to a common source line CSL…the semiconductor memory device may apply the erase voltage Verase to a node MTSRC coupled to the common source line CSL…”) that is a target voltage level, and wherein the second period (t1-t2 in figure 7) starts before the level of the voltage applied to the common source line reaches the erase voltage level.
Regarding claim 16, Lee teaches the erasing method of claim 15, wherein a level of the first bias voltage (pre-PGM in figure 7) is higher than a level of the voltage applied to the common source line in the first period (t0-t1 in figure 7).
Regarding claim 17, Lee teaches the erasing method of claim 15, wherein a number of the first word lines (e.g., WL1/WL2 in figure 5) is less than a number of the second word lines (e.g., WLn-2/WLn-1/WLn in figure 5).
Allowable Subject Matter
Claims 4-7, 11-14, 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The closest prior art to the present invention is Lee PG PUB 20180158505 (hereinafter Lee).
Lee discloses a semiconductor memory device may include a memory cell array including a plurality of memory blocks, each including dummy cells coupled to dummy word lines and normal memory cells coupled to normal word lines, a peripheral circuit configured to perform an erase operation on a memory block selected from among the plurality of memory blocks and control logic configured to control the peripheral circuit, during the erase operation, to apply a pre-program voltage pulse to the dummy word lines and the normal word lines, and to control application of dummy word line voltages to the dummy word lines based on Erase-Write (EW) cycling information while applying an erase voltage to a common source line of the selected memory block, wherein the EW cycling information indicates a number of erase-write cycles of the selected memory block.
Regarding claims 4, 11, 18, the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: the dummy word line is floating in a third period after the second period.
Regarding claims 5, 12, 19, the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: the first period ends and the second period starts at a time at which a gate induced drain leakage current is generated in the ground erase control transistor.
Regarding claims 6, 13, 20, the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: the row decoder is configured to apply the first bias voltage to the first word lines until a gate induced drain leakage current is generated in the ground erase control transistor.
Regarding claims 7, 14 the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: the row decoder is configured to apply the first bias voltage to the dummy word line until a gate induced drain leakage current is generated in the ground erase control transistor.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIAOCHUN L CHEN whose telephone number is (571)272-0941. The examiner can normally be reached on M-F: 9AM-5:00PM.
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/XIAOCHUN L CHEN/Examiner, Art Unit 2824
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