DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the amplifier comprises “a differential amplifier” recited in claims 11, 13, and 16 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The abstract of the disclosure is objected to because the content of the abstract is not consistence with the claims and the discussion of the specification. See the suggestion below. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
ABSTRACT
Systems, circuits, and methods for amplifying signals are provided. A receiver circuit may include an amplifier that amplifies an input signal received at an input node of the amplifier and provides an amplified version of the input signal as an output signal at an output node of the amplifier. The receiver circuit may further include at least one Continuous-Time Linear Equalizer (CTLE) circuit component connected with the amplifier, the CTLE circuit component providing an ultra-wide dynamic peaking control range for the amplifier.
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
The claimed subject matter, which recites that “the amplifier comprises a differential amplifier” in claims 11, 13, and 16, lacks clear antecedent basis in the specification.
Claim Objections
Claims 1-19 are objected to because of the following informalities:
1. (Proposed Amendment) A circuit, comprising:
an amplifier that amplifies an input signal received at an input node of the amplifier and provides an amplified version of the input signal as an output signal at an output node of the amplifier; and
at least one Continuous-Time Linear Equalizer (CTLE) circuit component connected with the amplifier, wherein the least one CTLE circuit component provides an ultra-wide dynamic peaking control range for the amplifier.
11. (Proposed Amendment) The circuit of claim 1, wherein the amplifier comprises a differential amplifier and wherein the at least one CTLE circuit component comprises a variable degeneration capacitor circuit that adds a variable degeneration capacitance to the amplifier.
13. (Proposed Amendment) The circuit of claim 1, wherein the amplifier comprises a differential amplifier and wherein the at least one CTLE circuit component comprises a variable shunt capacitor circuit connected at an emitter of the differential amplifier.
14. (Proposed Amendment) The circuit of claim 13, wherein the at least one CTLE circuit component further comprises an emitter follower circuit and wherein the variable shunt capacitor circuit is connected at an input of the emitter follower circuit.
15. (Proposed Amendment) A system, comprising:
a receiver circuit connected between a communication channel and a deserializer, wherein the receiver circuit comprises:
an amplifier; and
at least one Continuous-Time Linear Equalizer (CTLE) circuit component connected with the amplifier, wherein the least one CTLE circuit component provides an ultra-wide dynamic peaking control range for the amplifier.
Claims 2-10 and 12 depend either directly or indirectly from claim 1, therefore they are also objected.
Claims 16-19 all depend from claim 15, therefore they are also objected.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 12 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 is vague and indefinite because it improperly depends on itself.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Delshadpour et al. (US 2024/0154608 A1), hereinafter “Delshadpour”.
Delshadpour illustrates a wideband communication circuit in FIG. 2 in the form of a linear redriver without a gain stage. FIG. 3 shows an input/output stage of the wideband communication circuit of FIG. 2.
FIG. 4 depicts a wideband level shifter 400 which provides buffer with DC level shift function for a wide-band or narrow-band system. The wideband level shifter 400 includes a resistive/low-frequency path 430 with DC level shifting for a low-frequency component of an incoming signal with an input voltage, Vin, received through an input terminal/pin 402 of the level shifter 400 and a capacitive/high-frequency path 440 for a high-frequency component of the incoming signal. As shown in FIG. 4, the level shifter 400 includes a transistor 410, which can also be referred to as the transistor, Qi, to provide an extra DC level shift when the transistor 410 is biased with low current to pass the low-frequency portion of the incoming signal. The transistor 410 can be implemented using bipolar or complementary metal-oxide-semiconductor (CMOS) transistor technology. In an example, the transistor 410 is a bipolar junction transistor (BJT), which can be used as an emitter follower or a common collector amplifier. In another example, the transistor 410 is a metal-oxide-semiconductor field-effect transistor (MOSFET) (e.g., an N-channel MOSFET), which can be used as a source follower or a common drain amplifier. In addition, the level shifter 400 includes a capacitor 416, which is connected between a terminal of the transistor 410 and an output terminal/pin 426 of the level shifter 400 to pass the high-frequency component of the incoming signal (considering the resistor 424 is in the path). The level shifter 400 may use DC programming/shifting to set the required DC bias voltage of a next stage, which may be a linear CTLE, a TX driver, or any needed stage. In some embodiments, the level shifter 400 implements a resistor divider 420 with switchable resistors 422-1, 422-2, 422-3, 422-4, 422-5, 422-6 to provide a programmable DC loss or a programmable DC gain for, for example, a high-speed repeater. For example, with combination of a switched resistor bank, the level shifter 400 can provide DC gain programming and peaking gain boost, which can be used for trimming of DC/peaking gain of a CTLE. The level shifter 400 can also help overall high frequency gain boosting if needed because the level shifter 400 can act as a passive CTLE in which DC level shifting and isolation of the CTLE from input pins in wireline communication is needed for most applications. The level shifter 400 can also provide DC shift and isolation from a CTLE to a TX driver or a gain stage after a CTLE. Compared to a typical active buffer or level shifter, the level shifter 400 exhibits lower power consumption, which is suited for low power applications. See paragraph [0046].
Regarding claim 1, Delshadpour illustrates a system (wide band communication system, par. [0001]), comprising: a receiver circuit (CTLE 200 of a receiver front end, par. [0035]) connected between a communication channel and a deserializer (not shown), wherein the receiver circuit comprises: an amplifier (Tx pre-driver or driver 204); and at least one Continuous-Time Linear Equalizer (CTLE) circuit component (CTLE buffer 202) connected with the amplifier, wherein the CTLE circuit component provides an ultra-wide dynamic peaking control range for the amplifier.
Applicant notes that although Delshadpour may not disclose the exact wording recited in claim 15, the corresponding drawings and associated discussions inherently disclose these features to a person of ordinary skill in the art.
It is well known in digital communications that a receiver circuit sits between a communication channel and a deserializer. This sequence forms the standard front-end architecture for processing high-speed serial data.
As mentioned above in at least paragraph [0046], the CTLE with this exact topology inherently satisfies and fits well within claim 15 for at least the following reasons:
Linear Amplification: The BJT operates in its active region as a linear amplifier.
At least one CTLE component: By varying the DC attenuation while keeping peaking gain fixed or vice versa, the circuit provides DC gain programming and peaking boost. This tunability allows the CTLE to dynamically equalize channel loss.
Buffer Isolation: An emitter follower (common collector) has high input impedance and low output impedance. It acts as a buffer, preventing the tuning circuits from loading down or distorting the main amplifier.
Independent Trimming: By using the transistor to isolate the DC attenuation stages (like resistor-capacitor trimming networks) from the AC peaking stages, the circuit can adjust the DC operating point and broadband gain boost independently.
Ultra-wide Peaking Control Range: Separating the control of DC attenuation and high-frequency peaking removes the trade-offs found in simpler topologies, resulting in an ultra-wide control range.
Regarding apparatus claim 1, the features recited therein are encompassed by the apparatus of claim 15 for the same reasons discussed above.
Regarding method claim 20, the steps recited correspond to the apparatus features of claim 15 for the same reasons detailed above.
Regarding claim 2 and 19, in RF and high-speed analog design, an ultra-wide dynamic peaking control range is widely and inherently considered to be significantly greater than 2 dB (often falling in the 10dB to 20dB range) at peaking frequencies exceeding 10GHz. This is well-established in high-speed optical communications and microwave engineering.
Regarding claims 3-6 and 18, as described in claim 15 above, it is inherent, well known and foundational in analog and mixed-signal integrated circuit design that CTLE circuits are built using these exact overlapping topologies. This is because no single, isolated component can effectively combat high-frequency attenuation, impedance mismatches, and process variations.
RC Circuit (Resistor-Capacitor): Provides the fundamental frequency peaking. By utilizing an RC network for source degeneration, the circuit decreases local negative feedback at higher frequencies, causing gain to increase right at the Nyquist frequency to compensate for channel loss.
Variable Degeneration & Shunt Capacitors: Allows for tunability and calibration. Because transmission channels (like PCB traces or optical fibers) have unpredictable and varying lengths, variable capacitors allow engineers to dynamically adjust the peaking frequency and gain.
Emitter Follower Circuit: Acts as a voltage buffer and level shifter. It provides high input impedance and low output impedance, which prevents the equalization stage from loading down the previous amplifier stage while driving subsequent high-capacitance loads.
Feedback Circuit (Shunt/Active Feedback): Extends bandwidth and flattens gain. Introducing feedback creates additional high-frequency zeros, compensating for the natural parasitic roll-off of the amplifying transistors.
Regarding claim 7, it is inherent and well-known in the art that Continuous-Time Linear Equalization (CTLE) circuit components, such as active transconductance stages, utilize feedback (e.g., capacitive or resistive) to shape the circuit's frequency response.
Creating Zeros & Frequency Peaking: A transmission channel typically acts as a low-pass filter, severely attenuating higher-frequency signal components. By applying local feedback around an amplifier, designers create a zero in the transfer function. This causes frequency peaking, boosting the gain at higher frequencies to perfectly offset the channel’s losses.
Bandwidth Extension: Feedback, specifically source/emitter degeneration lowers the effective gain at low frequencies while extending the usable amplifier bandwidth to accommodate multi-gigabit/s data rates.
Adjustability and Control: Integrating tunable feedback circuits (such as variable resistors and capacitors) allows designers to dynamically adapt the CTLE to varying cable lengths, channel losses, and different data rates (e.g., in PCIe or SerDes links).
Regarding claim 8, as described above, the claimed subject matter of claim 8 is inherent and a well-known electronic topology. It describes a transistor (such as a BJT) amplifier with collector-to-base (shunt) negative feedback, combined with an active element in the feedback loop.
The Main Transistor: A bipolar junction transistor (BJT) acting as the amplifying element, typically configured as a common-emitter amplifier.
The Feedback Loop: A resistor/transistor network is connected directly between the output (collector) and the input (base).
The Feedback Transistor: The feedback circuit uses a transistor operating in its linear region (also known as the active region) with a controlled voltage at its gate (or base).
The Bias Resistor: A bias resistor sets the specific operating voltage at the control terminal of the feedback transistor to keep it in the linear region.
Regarding claim 9, it is fundamentally well known in the art that feedback circuits (such as collector-feedback bias) often utilize an isolating capacitor in the feedback path.
Regarding claim 10, it is well known in analog electronic design by adjusting a transistor's bias voltage changes its operating characteristics, which directly impacts an amplifier's gain (amplification) and its frequency response (including peaking).
Regarding claims 11, 12, and 16, it is well-known in the art that amplifiers (such as continuous-time linear equalizers, or CTLEs) utilize differential amplifier topologies and employ tunable degeneration capacitors or switchable capacitor networks to calibrate high-frequency performance.
Regarding claims 13 and 14, as described in claim 15 above, it is a well-known, foundational circuit architecture in high-speed analog and RF design. It is frequently employed in Continuous-Time Linear Equalizers (CTLE) to provide adjustable high-frequency boosting, such as in high-speed serial links (e.g., PCIe, USB, Ethernet) and optical receivers.
The Core: A differential amplifier utilizes emitter (or source) degeneration to control gain and bandwidth.
The CTLE Component: A variable shunt capacitor, often accompanied by a tuning resistor, is connected to the emitters.
The Emitter Follower: Placed at the emitters of the main differential pair, the shunt capacitor connects to the input of this follower rather than directly to ground.
Regarding claim 17, as described in at least paragraph [0046], it is the foundational principle of modern electronics that an amplifier circuit comprises either a Bipolar Junction Transistor (BJT) or a Field-Effect Transistor (FET). These components are chosen because they possess a property called gain, meaning they can use a small, weak input signal to precisely control and produce a much larger, amplified output signal.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Geng et al. (US 2020/0153395 A1) relates a wide band communications circuit buffer includes a pair of NPN bipolar transistor emitter followers deployed as a voltage buffer and disposed at inputs before and outputs after an equalization module, and a pair of diode connected NPN transistors deployed as a level shifter and disposed following the emitter followers before an output of the wide band driver to keep an output level at the output of the wide band buffer close to a desired level. Resistors connected between emitters and a VEE terminal can be used to further adjust the DC level. An LC tank filter can be provided between emitters of the voltage buffer components and the circuit's outputs to pass and boost high frequency signals provided to next stage components. The wide band buffer is, inter alia, appropriate for use in providing a DC level shift function as used in wired data communication systems circuitry.
Delshadpour et al. (US 2021/0359883 A1) relates to a high bandwidth continuous time linear equalization (HBCTLE) circuit includes a continuous time linear equalization (CTLE) circuit and a gain circuit coupled with an output of the CTLE circuit.
Delshadpour et al. (US 2024/0154919 A1) relates to a communications circuit, including: a buffer having a buffer input and a buffer output; wherein the buffer includes a first path and a second path; wherein the first path includes, a first resistor coupled to the buffer input; a second resistor coupled to the buffer output; a current source having a first end and a second end; wherein the first resistor and the second resistor are coupled to a mid-point; wherein the first end of the current source is coupled to the mid-point; and wherein the second path includes a capacitor having a first end coupled to the buffer input and a second end coupled to the buffer output.
Geng et al. (US 2024/0223411 A1) relates to an equalizer includes a first signal path segment that includes a first plurality of serially connected transistors and current sources, a second signal path segment that includes a second plurality of serially connected transistors and current sources, and at least one termination resistor connected to the first and second signal path segments. The first plurality of serially connected transistors and current sources includes a first current source and a second current source connectable to a reference voltage and a first transistor and a second transistor connected between input terminals of the equalizer and the first and second current sources, where the first signal path segment further includes at least one resistor connected between the first and second current sources.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Young T. Tse whose telephone number is (571)272-3051. The examiner can normally be reached Mon-Fri 10:30am-7pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chieh M Fan can be reached at 571-272-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Young T. Tse/Primary Examiner, Art Unit 2632
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