DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 4, 5, 10 and 14-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II and Species A-E and G, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/5/2025
Applicant’s election without traverse of Invention I and Species F drawn to claims 1-3, 6-9 and 11-13 in the reply filed on 12/5/2025 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3, 6-9 and 11-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As to claim 1, it is unclear what is meant by a “virtual load”. According to the specification in paragraph [0007], “the virtual load unit may include a first switch and a first resistor in series between the third power line and ground potential”. This is indefinite as “may include” is broad and may include other elements as well. It is not clear where are the boundaries of a virtual load. Claims 2, 3, 6-9 and 11-13 are dependent on claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Pub. No. 2021/0065628 A1 to Kim et al. in view of U.S. Patent Pub. No. 2021/0264847 A1 to Jeong et al.
As to claim 1, Kim discloses a display device comprising:
a pixel including a light emitting element, a pixel circuit for controlling a current flowing from a first power line to a second power line via the light emitting element, and an initialization transistor connected between an anode electrode of the light emitting element and a third power line to which a voltage of initialization power is supplied (Fig. 3, paragraph 0071, pixel (PX), light emitting element (LD), first power line (ELVDD), second power line (ELVSS), initialization transistor (T7), third power line (VINTL)); and
a power supply for supplying the initialization power (Fig. 1 and 2, paragraphs 0049 and 0067), where power supply (70) supplies initialization power via initialization voltage (VINT)),
wherein the power supply comprises:
an initialization power supply for supplying the initialization power (Fig. 1 and 2, paragraphs 0049 and 0067, where VINT controller (73) is the initialization power supply).
Kim is deficient in disclosing a virtual load unit connected to the third power line and providing an additional load to the third power line.
However, Jeong discloses a virtual load unit connected to the third power line and providing an additional load to the third power line (Fig. 9, paragraphs 0139-0144, where the control circuit (910) is connected to the third power line (PL3) and provides an additional load by adjusting the initialization voltage (VINT)).
At the time of filing, it would have been obvious to a person of ordinary skill in the art to have modified the power supply for supplying an initialization power as taught by Kim by including a virtual load connected to a power line as taught by Jeong. The suggestion/motivation would have been in order to control the initialization voltage to the pixel circuit (Jeong, paragraphs 0139-0144).
As to claim 13, Kim discloses the display device, wherein the initialization transistor is turned on in response to a first scan signal being supplied to a first scan line, and
the first scan signal is supplied at least twice during one frame period (Fig. 6, paragraphs 0088-0097, where scan signal (SCAN1) is provided at least twice during “p” frame period).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Pub. No. 2021/0065628 A1 to Kim et al. in view of U.S. Patent Pub. No. 2021/0264847 A1 to Jeong et al. as applied to claim 1 above, and further in view of U.S. Patent Pub. No. 2006/0227126 A1 to Kawagoshi.
As to claim 2, Kim and Jeong are deficient in disclosing the display device, wherein the virtual load unit includes a first switch and a first resistor connected in series between the third power line and a ground potential.
However, Kawagoshi discloses the display device, wherein the virtual load unit includes a first switch and a first resistor connected in series between the third power line and a ground potential (Fig. 2 and 3, paragraphs 0028-0029, where voltage generation circuit (200) includes voltage diving circuit (202) with several resistors and selector (204) with several switches).
At the time of filing, it would have been obvious to a person of ordinary skill in the art to have modified the power supply as taught by Kim and Jeong by including a virtual load with a switch and resistor connected in series as taught by Kawagoshi. The suggestion/motivation would have been in order to control the output voltage to the pixel circuit (Kawagoshi, paragraphs 0028-0029).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Pub. No. 2021/0065628 A1 to Kim et al. in view of U.S. Patent Pub. No. 2021/0264847 A1 to Jeong et al. in view of U.S. Patent Pub. No. 2006/0227126 A1 to Kawagoshi. as applied to claim 2 above, and further in view of U.S. Patent Pub. No. 2019/0304365 to Hyun et al.
As to claim 3, Kim, Jeong and Kawagoshi are deficient in disclosing the display device, further comprising: a timing controller for controlling the virtual load unit.
However, Hyun discloses the display device, further comprising: a timing controller for controlling the virtual load unit (Fig. 1, paragraph 0028, where timing controller (160) controls power supply (150)).
At the time of filing, it would have been obvious to have modified the power supply as taught by Kim, Jeong and Kawagoshi by including a timing controller as taught by Hyun. The suggestion/motivation would have been in order to control the timing of the voltage sent to the voltage lines of the pixels (Hyun, paragraph 0041).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Pub. No. 2021/0065628 A1 to Kim et al. in view of U.S. Patent Pub. No. 2021/0264847 A1 to Jeong et al. in view of U.S. Patent Pub. No. 2006/0227126 A1 to Kawagoshi in view of U.S. Patent Pub. No. 2019/0304365 to Hyun et al. as applied to claim 3 above, and further in view of U.S. Patent Pub. No. 2015/0213775 A1 to Lee et al.
As to claim 6, Kim, Jeong, Kawagoshi and Hyun are deficient in disclosing the display device, wherein the first resistor is a digital resistor.
However, Lee discloses the display device, wherein the first resistor is a digital resistor (Fig. 6, paragraph 0120, digital resistors (DR1, DR2)).
At the time of filing, it would have been obvious to a person of ordinary skill in the art to have modified the power supply as taught by Kim, Jeong, Kawagoshi and Hyun by including a digital resistor as taught by Lee. The suggestion/motivation would have been in order to control the resistance digitally (Lee, paragraph 0120).
Allowable Subject Matter
Claims 7-9, 11 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record alone, or in combination, fail to teach, disclose, or render obvious, “wherein the timing controller controls turn-on and turn-off of the first switch and a resistance value of the first resistor so that a load on the third power line is constant”, in combination with the other limitations set forth in claim 7.
The prior art of record alone, or in combination, fail to teach, disclose, or render obvious, “wherein the power supply further comprises sensing unit for sensing at least one of a voltage and a current of the third power line and controlling the virtual load unit in response to at least one of the sensed voltage and current”, in combination with the other limitations set forth in claim 8.
Claims 9, 11 and 12 are dependent on claim 8.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANEETA YODICHKAS whose telephone number is (571)272-9773. The examiner can normally be reached Monday-Friday 9-5.
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ANEETA YODICHKAS
Primary Examiner
Art Unit 2627
/ANEETA YODICHKAS/
Primary Examiner, Art Unit 2627