Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
1. Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Horley et al (US 2023/0214224, herein Horley) in view of Gschwind et al (US 2015/0309812, herein Gschwind).
Regarding claim 1, Horley teaches a system for executing a software program, the system comprising a plurality of processing units and at least one hardware processor (Fig 1, [0062], processor) configured to:
select a set of blocks from at least one set of blocks, each set comprising a calling block and a target block of a plurality of blocks of an intermediate representation of the software program, the set selected according to at least one statistical value, where the at least one statistical value is collected while executing the software program ([0056], [0060], [0081], call stack used to maintain values when transferring between program subroutines via call (entry) and return (exit));
describing at least one value of the software program at an exit of the calling block (out-value) and at least one other value of the software program at an entry to the target block (in-value) ([0037-0038], [0066], generating control transfer information during program execution, [0113], dynamic binary translation of instructions);
generate a calling set of executable instructions using the calling block and the control- transfer information of the selected set of blocks ([0056], [0066], [0081], generating control transfer information and use of call stack to move between program subroutines); and
configure at least one of a calling processing unit of the plurality of processing units and a target processing unit of the plurality of processing units to execute the calling set of executable instructions and the target set of executable instructions, respectively ([0068], [0070], execution of instructions on processor pipeline).
Horley fails to teach generating a target set of executable instructions using the target block and control-transfer information of the selected set of blocks.
Gschwind teaches a system configured to generate a target set of executable instructions using target block and control-transfer information of a selected set of blocks ([0008], [0020], [0028-0030], compiling of instructions with TOC for function calls, branch information included in linked entry or exit point code).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Horley and Gschwind to utilize in the runtime profiling techniques of Horley in the instruction generation stage of processing. While Horley does not explicitly state that the control transfer and other function call related information may be incorporated at compile time or another instance of instruction generation, such as decoding microoperations from instructions, one of ordinary skill in the art would understand that this is a routine and conventional aspect of the microprocessor art, and therefore utilizing these techniques during compilation and linking, as described by Gschwind, would merely entail a simple substitution of known prior art elements to achieve predictable results, and would have been obvious to one of ordinary skill in the art.
Regarding claim 2, the combination of Horley and Gschwind teaches the system of claim 1, wherein the at least one hardware processor is further configured to select the set of blocks, generate the target set of executable instructions, generate the calling set of executable instructions, configure the calling processing unit and configure the target processing unit while executing the software program (Horley [0066], profiling during processor operation & Gschwind [0021], [0028-0029], generating stack TOC during runtime).
Regarding claim 3, the combination of Horley and Gschwind teaches the system of claim 1, wherein the at least one hardware processor is further configured to execute the software program in each of at least two iterations, comprising a first iteration and a second iteration; and wherein the at least one hardware processor is additionally further configured to select the set of blocks, generate the target set of executable instructions, generate the calling set of executable instructions, configure the calling processing unit and configure the target processing unit after executing the software program in the first iteration and before executing the software program in the second iteration (Horley [0066-0067], profiling of execution during first iteration, [0093], use of profiled information in subsequent execution of instruction in later iteration).
Regarding claim 4, the combination of Horley and Gschwind teaches the system of claim 1, wherein the calling processing unit has a first computer architecture; wherein the target processing unit has a second computer architecture; and wherein the first computer architecture is different from the second computer architecture (Horley [0113], different hardware architectures).
Regarding claim 5, the combination of Horley and Gschwind teaches the system of claim 1, wherein the calling processing unit executes a first operating system; wherein the target processing unit executes a second operating system; and wherein the first operating system is different from the second operating system (Horley [0113-0114], dynamic translation between host or other operating systems & Gschwind [0003], use of multiple operating systems via binary interface).
Regarding claim 6, the combination of Horley and Gschwind teaches the system of claim 1, wherein at least one of the calling processing unit and the target processing unit does not execute an operating system (Horley [0113], simulated processing environment without separate OS).
Regarding claim 7, the combination of Horley and Gschwind teaches the system of claim 1, wherein executing the calling set of executable instructions by the calling processing unit comprises setting the out-value described by the control-transfer information to an identified value; and wherein the target processing unit retrieves the identified value when accessing the in-value while executing the target set of executable instructions, where the in-value is described by the control-transfer information (Gschwind [0030] & Horley [0056], [0060], [0081], call stack used to maintain values when transferring between program subroutines via call (entry) and return (exit)).
Regarding claim 8, the combination of Horley and Gschwind teaches the system of claim 1, wherein the control-transfer information is one or more of: independent of a first identified computer architecture of the calling processing unit; independent of a second identified computer architecture of the target processing unit; independent of a first identified operating system executed by the calling processing unit; and independent of a second identified operating system executed by the target processing unit. (Horley [0056], [0081] & Gschwind [0030], profiling information independent of any OS or specific architecture).
Regarding claim 9, the combination of Horley and Gschwind teaches the system of claim 1, wherein the control-transfer information comprises at least one register of a processing circuitry (Gschwind [0020], TOC register).
Regarding claim 10, the combination of Horley and Gschwind teaches the system of claim 1, wherein the control-transfer information comprises at least one memory offset value (Gschwind [0005], [0029-0030], claim 3, use of offset value for function address register).
Regarding claim 11, the combination of Horley and Gschwind teaches the system of claim 1, wherein the control-transfer information comprises at least one type value associated with the out-value, and at least one other type value associated with the in-value (Horley [0090], profiling based on instruction type, Gschwind [0022], inserting TOC data to entry or exit based type of called function).
Regarding claim 12, the combination of Horley and Gschwind teaches the system of claim 1, wherein the control-transfer information comprises an amount of variables (Gschwind [0005], TOC variable values).
Regarding claim 13, the combination of Horley and Gschwind teaches the system of claim 1, wherein the control-transfer information comprises at least one computer instruction (Gschwind [0022], [0030], inserting of instructions by linker),
Regarding claim 14, the combination of Horley and Gschwind teaches the system of claim 1, wherein the control-transfer information is generated before executing the software program; and wherein the at least one hardware processor is further configured to select the target processing unit from the plurality of processing units after collecting the at least one statistical value (Gschwind [0029-0030], compile-time instruction and information generation & Horley [0066-0067], runtime profiling).
Regarding claim 15, the combination of Horley and Gschwind teaches the system of claim 14, wherein the at least one hardware processor is further configured to generate the target set of executable instructions according to the selected target processing unit (Horley [0115], architecture-specific simulation & Gschwind [0036], generating specific ISA instructions).
Regarding claim 16, the combination of Horley and Gschwind teaches the system of claim 1, wherein the at least one hardware processor is further configured to add the control-transfer information to the intermediate representation of the software program (Horley [0052], [0068], software defined state including profiled call stack buffer)
Regarding claim 17, the combination of Horley and Gschwind teaches the system of claim 1, herein the at least one hardware processor is further configured to: generate at least one executable software object for executing the software program; and at least one of: add the control-transfer information to the at least one executable software object; and add the control-transfer information to at least one file associated with the at least one executable software object (Horley [0052], [0068], software defined state including profiled call stack buffer & Gschwind [0025], [0030], compile time addition of TOC contents).
Regarding claim 18, the combination of Horley and Gschwind teaches the system of claim 1, wherein the at least one hardware processor is further configured to: for the selected set of blocks, generate the control-transfer information of the selected set of blocks to further describe at least one additional value of the software program at another exit of the target block and at least one additional other value of the software program at another entry to another block of the selected set of blocks (other target block); generate another target set of executable instructions using the other target block and the control-transfer information of the selected set of blocks; and configure the calling processing unit of the plurality of processing units to execute the other target set of executable instructions (Horley [0052], [0068], [0081] & Gschwind [0003], [0022], [0030], multiple subroutines of executable instructions generated by compiler and runtime profiler to be executed by software program).
Claim 19 refers to a method embodiment of the system embodiment of claim 1. Therefore, the above rejection for claim 1 is applicable to claim 19.
Claim 20 refers to a program product embodiment of the system embodiment of claim 1. Therefore, the above rejection for claim 1 is applicable to claim 20.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Bitla (US 2023/0004487) discloses a processor for generating call graphs for subroutine entry and exit points.
Evers (US 2019/0384612) discloses a processor for tracking address offsets and other control transfer information.
Winkel (US 2016/0266905) discloses a processor with a dynamic binary translator to assign code to logical threads in basic blocks with entry and exit points.
Hayashizaki (US 2013/0055226) discloses a processor for profiling variable types, branch directions, and entry and exit frequencies of code traces.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J METZGER whose telephone number is (571)272-3105. The examiner can normally be reached Monday-Friday 8:30-5.
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/MICHAEL J METZGER/ Primary Examiner, Art Unit 2183
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