DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 01/10/2025 and 09/30/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 11 and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2019/0378855 A1).
Regarding claim 1, Kim teaches a semiconductor memory device comprising:
a substrate including a first stacked region, a second stacked region, and a pad region, the pad region being between the first stacked region and the second stacked region in a first horizontal direction (Fig. 4, first stack MA1, second stack MA2 and pad region C-ST1 and C-ST2);
a plurality of word lines extending from the pad region toward each of the first stacked region and the second stacked region in the first horizontal direction, the plurality of word lines spaced apart from each other in a vertical direction (Fig. 4, word lines extending from the pad region toward the stacked regions MA1 and MA2);
a plurality of bit lines extending in the vertical direction, the plurality of bit lines spaced apart from each other in the first horizontal direction in each of the first stacked region and the second stacked region (bit lines BL extend in the vertical direction in each of the first and second stacks MA1 and MA2);
a plurality of memory cells interposed between the plurality of word lines and the plurality of bit lines in each of the first and second stacked regions (Fig. 4, memory cells formed at the intersection of the word lines and the bit lines);
a word line contact connected to a corresponding one of the plurality of word lines at the pad region (Fig. 1, G-PA and G_Ia); and
a sub-word line driver connected to the word line contact (Fig. 1, Row decoder 32 drives signals to the word lines).
Regarding claims 11 and 18, the claims have similar limitations as claim 1 above. Therefore, the claims are rejected under the same grounds of rejection.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2023/0005934 A1).
Regarding claim 1, Kim teaches a semiconductor memory device comprising:
a substrate including a first stacked region (Fig. 4, area above SWD1), a second stacked region (area above SWD2), and a pad region, the pad region being between the first stacked region and the second stacked region in a first horizontal direction (Fig. the pad region is the area under the label DWL);
a plurality of word lines extending from the pad region toward each of the first stacked region and the second stacked region in the first horizontal direction, the plurality of word lines spaced apart from each other in a vertical direction (Fig. 4, the word lines WLs are extended into the first and second stacked regions);
a plurality of bit lines extending in the vertical direction, the plurality of bit lines spaced apart from each other in the first horizontal direction in each of the first stacked region and the second stacked region (bit lines BL extend in the vertical direction in each of the first and second stacks regions);
a plurality of memory cells interposed between the plurality of word lines and the plurality of bit lines in each of the first and second stacked regions (Fig. 4, memory cells formed at the intersection of the word lines and the bit lines);
a word line contact connected to a corresponding one of the plurality of word lines at the pad region (Fig. 4, DWL); and
a sub-word line driver connected to the word line contact (Fig. 6, sub word line driver 200).
Regarding claim 2, Kim further teaches the semiconductor memory device of claim 1, wherein a portion of a specific word line of the plurality of word lines in the first stacked region and a portion of the specific word line in the second stacked region are electrically connected to the sub-word line driver through the word line contact that is connected to a portion of the specific word line in the pad region (Fig. 4).
Regarding claim 3, Kim further teaches the semiconductor memory device of claim 1, wherein each of the plurality of memory cells includes a cell transistor and an information storage element, and the cell transistor includes a semiconductor pattern extending from a corresponding one of the plurality of bit lines in a second horizontal direction different from the first horizontal direction (See Fig. 2A).
Regarding claim 4, Kim further teaches the semiconductor memory device of claim 3, wherein the semiconductor pattern includes a source region connected to the corresponding one of the plurality of bit lines, a channel region, and a drain region connected to the information storage element, the source region, the channel region, and the drain region being sequential from the corresponding one of the plurality of bit lines in the second horizontal direction (See Fig. 2A).
Regarding claim 5, Kim further teaches the semiconductor memory device of claim 4, wherein the information storage element includes a capacitor including a first electrode connected to the drain region, a capacitor dielectric film covering the first electrode, and a second electrode covering the capacitor dielectric film (Fig. 2A, capacitor CAP).
Regarding claim 6, Kim further teaches the semiconductor memory device of claim 4, wherein the semiconductor pattern passes through each of the plurality of word lines, and the channel region is a portion of the semiconductor pattern that passes through each of the plurality of word lines (Fig. 2A).
Regarding claim 7, Kim further teaches the semiconductor memory device of claim 1, wherein a first group of memory cells adjacent to the pad region, from among the plurality of memory cells in the first stacked region, and a second group of memory cells adjacent to the pad region, from among the plurality of memory cells in the second stacked region, are configured to be selected by the sub-word line driver (Fig. 4).
Regarding claim 8, Kim further teaches the semiconductor memory device of claim 1, wherein each of the plurality of word lines extends in the first horizontal direction through the pad region from the first stacked region to the second stacked region (Fig. 4, word lines WL).
Regarding claim 9, Kim further teaches the semiconductor memory device of claim 8, wherein an extension length of each of the plurality of word lines in the first horizontal direction is same (Fig. 4, extension length each of the WLs is the same).
Regarding claim 10, Kim further teaches the semiconductor memory device of claim 9, wherein the word line contact contacts an electrically connected word line among the plurality of word lines spaced apart from each other in the vertical direction, does not contact the other word lines among the plurality of word lines, and passes through one or more word lines being above the electrically connected word line among the plurality of word lines (Fig. 4, word line contact contacts WLP1 and WLP2).
Regarding claims 11-20, the claims have similar limitations as claims 1-10. Therefore, the claims are rejected under the same grounds of rejection as the claims above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAMDAN N ALROBAIE whose telephone number is (571)270-7099. The examiner can normally be reached Monday to Thursday (8AM till 6PM).
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/Khamdan N. Alrobaie/ Primary Examiner, Art Unit 2824
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