Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments and Arguments
Amendments and arguments filed on 02/11/2026 have been fully considered and are not found to place the application in a condition for allowance.
Regarding the objections to the drawings, a replacement sheet for fig. 6 is required wherein N2 is shown to reflect the inversion between N1 and N2. Currently, N1 and N2 signals are not shown as mirror images of each other.
Regarding the amended limitations, the Office agrees that Park does not specifically teach that the sub-pixels sharing the PAM unit are of different colors. However, based on an updated prior art search, such a limitation is found to be disclosed in the prior art. Accordingly, such limitations are found to be obvious in view of the prior art and the amended claims are not found to be patentable.
Drawings
The drawings are objected to because fig. 6, does not appear to correctly represent the waveform of N2 per the specification. According to the circuit of fig. 5, N2 is an inverted form of N1, however, fig. 6 does not show such an inversion during and before the P1 period. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 5-6, 8-12, 14-15, and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over by Park et al., US 2025/0174178 A1, hereinafter “Park”, in view of Shigeta et al., US 2022/0301500 A1, hereinafter “Shigeta ‘500”.
Regarding claim 1, Park teaches a pixel (fig. 2, GSP1, ¶ 72), comprising: a first sub-pixel which displays a first color (fig. 10, PWM1, ¶ 78); and a second sub-pixel which displays a second color (fig. 10, PWM2, ¶ 78; note that each EL displays a color), wherein each of the first sub-pixel and the second sub-pixel includes: a light-emitting element through which a driving current flows (fig. 10, EL of each PWM unit, ¶ 74); and a pulse width modulator which controls a width of the driving current (fig. 10, see other elements of each PWM unit, ¶ 74), and the first sub-pixel and the second sub-pixel share a pulse amplitude modulator which controls an amplitude of the driving current (fig. 10, PAM is shared by the PWM units, ¶ 73).
Park does not specifically teach that the first and second color are different.
Shigeta ‘500 teaches a shared PAM and pixel configuration similar to that of Park (fig. 7A, ¶ 125-126; wherein PAM 120-1 drives pixels of the same color in at least a portion of a column). Shigeta ‘500 further teaches in another embodiment that “each of the unit groups 100-1 to 100-3 included in the display module 1000 includes three different sub-pixel circuits such as R, G, and B” (fig. 7B, ¶ 127). In other words, Shigeta ‘500 clearly teaches that a pixel group 100-1 similar to GSP1 of Park, may include different color pixels.
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Park in view of Shigeta ‘500. The references teach PWM and PAM driving units for pixels of a display device and Shigeta ‘500 further teaches that a pixel group sharing the same PAM may include subpixels of different colors. One would have been motivated to make such a combination because Shigeta ‘500 teaches that “The R, G, and B sub-pixel circuits included in each unit group are included in one pixel region, rather than adjacent scan lines, and constitute one pixel” (see ¶ 128), thus forming and controlling a pixel including all the required color subpixels, thereby controlling the display device as taught by the references.
Regarding claim 11, Park teaches a pixel (fig. 2, GSP1, ¶ 72), comprising: a first sub-pixel which displays a first color (fig. 10, PWM1, ¶ 78); and a second sub-pixel which displays a second color (fig. 10, PWM2, ¶ 78; note that each EL displays a color), wherein each of the first sub-pixel and the second sub-pixel includes: a light-emitting element through which a driving current flows (fig. 10, EL of each PWM unit, ¶ 74); and a transistor which controls a width of the driving current in response to an emission signal (fig. 10, DT2 of each PWM unit, ¶ 74), and the first sub-pixel and the second sub-pixel share a pulse amplitude modulator which controls an amplitude of the driving current (fig. 10, PAM is shared by the PWM units, ¶ 73).
Park does not specifically teach that the first and second color are different.
Shigeta ‘500 teaches a shared PAM and pixel configuration similar to that of Park (fig. 7A, ¶ 125-126; wherein PAM 120-1 drives pixels of the same color in at least a portion of a column). Shigeta ‘500 further teaches in another embodiment that “each of the unit groups 100-1 to 100-3 included in the display module 1000 includes three different sub-pixel circuits such as R, G, and B” (fig. 7B, ¶ 127). In other words, Shigeta ‘500 clearly teaches that a pixel group 100-1 similar to GSP1 of Park, may include different color pixels.
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Park in view of Shigeta ‘500. The references teach PWM and PAM driving units for pixels of a display device and Shigeta ‘500 further teaches that a pixel group sharing the same PAM may include subpixels of different colors. One would have been motivated to make such a combination because Shigeta ‘500 teaches that “The R, G, and B sub-pixel circuits included in each unit group are included in one pixel region, rather than adjacent scan lines, and constitute one pixel” (see ¶ 128), thus forming and controlling a pixel including all the required color subpixels, thereby controlling the display device as taught by the references.
Regarding claim 17, Park teaches a display device (fig. 1, element 100, ¶ 55), comprising: a plurality of pixels (GSP, ¶ 72), each of the plurality of pixels configured per the pixel of claim 1 (see rejection of claim 1 provided above).
Regarding claims 2, 12 and 18, Park teaches that a frame period includes a first sub-frame period (fig. 11, frame period C-F, ¶ 157) and a second sub-frame period (fig. 11, frame period E-H, ¶ 157), the first sub-pixel displays the first color in the first sub-frame period (fig. 12D, ¶ 157), and the second sub-pixel displays the second color in the second sub-frame period (fig. 12E, ¶ 157).
Regarding claims 3 and 19, Park teaches that a first data voltage is applied to the pulse width modulator of the first sub-pixel in the first sub-frame period (¶ 169-171 wherein Data_PWM for PWM1 is applied), and a second data voltage is applied to the pulse width modulator of the second sub-pixel in the second sub-frame period (¶ 173 wherein Data_PWM for PWM2 is applied).
Regarding claim 5, Park teaches that the pulse amplitude modulator includes a current source (¶ 105).
Regarding claim 6, Park teaches that the pulse amplitude modulator is electrically connected to a line which transmits a high power voltage (fig. 10, PAM is connected to VDD), the light-emitting element is electrically connected to a line which transmits a low power voltage (EL connection to VSS), and the pulse width modulator is electrically connected between the pulse amplitude modulator and the light-emitting element (see fig. 10).
Regarding claim 8, Park teaches a third sub-pixel which displays a third color (fig. 10, PWM3, ¶ 78), wherein the third sub-pixel includes the light-emitting element and the pulse width modulator (fig. 3, see PWM3), and the first sub-pixel, the second sub-pixel, and the third sub-pixel share the same pulse amplitude modulator (fig. 10, PAM is shared by the PWM units, ¶ 73).
Regarding claim 9, Park teaches that a frame period includes a first sub-frame period (fig. 11, frame period C-F, ¶ 157), a second sub-frame period (fig. 11, frame period E-H, ¶ 157), and a third sub-frame period (fig. 11, frame period G-I, ¶ 157), the first sub-pixel displays the first color in the first sub-frame period (fig. 12D, ¶ 157), the second sub-pixel displays the second color in the second sub-frame period (fig. 12E, ¶ 157), and the third sub-pixel displays the third color in the third sub-frame period (fig. 12F, ¶ 157).
Regarding claim 10, Park teaches that a first data voltage is applied to the pulse width modulator of the first sub-pixel in the first sub-frame period (¶ 169-171 wherein Data_PWM for PWM1 is applied), a second data voltage is applied to the pulse width modulator of the second sub-pixel in the second sub-frame period (¶ 173 wherein Data_PWM for PWM2 is applied), and a third data voltage is applied to the pulse width modulator of the third sub-pixel in the third sub-frame period (¶ 175 wherein Data_PWM for PWM3 is applied).
Regarding claim 14, Park teaches that the transistor includes: a gate to receive the emission signal, a first terminal electrically connected to the pulse amplitude modulator, and a second terminal electrically connected to the light-emitting element (fig. 10, see configuration of DT2).
Regarding claim 15, Park teaches that the pulse amplitude modulator is electrically connected to a line which transmits a high power voltage (fig. 10, PAM is connected to VDD), the light-emitting element is electrically connected to a line which transmits a low power voltage (EL connection to VSS), and the transistor is electrically connected between the pulse amplitude modulator and the light-emitting element (see fig. 10).
Claims 4, 13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Park and Shigeta ‘500, as applied above, further in view of Shigeta et al., US 2018/0301080 A1, hereinafter “Shigeta ‘080”.
Regarding claims 4 and 20, Park teaches in another embodiment that the pulse width modulator includes: a first transistor (fig. 3, ST2) including a gate to receive a scan signal (SCAN2(n)), a first terminal to receive a data voltage (Data_PWM), and a second terminal electrically connected to a first node (N3); a capacitor (fig. 3, C2) including a first terminal to receive a sweep signal (Sween(n)) and a second terminal electrically connected to the first node (N3); a second transistor (fig. 3, DT2) including a gate electrically connected to a first node (N3), a first terminal electrically connected to the pulse amplitude modulator (N4), and a second terminal electrically connected to the light-emitting element (N5).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to modify the teachings of Park in view of the embodiments of figures 3 and 10. The embodiments teach different methods for compensating the threshold voltage of the driving transistor for each sub-pixel. Both embodiments teach independently controlling the light emission of each sub-pixel (¶ 97 for circuit configuration of fig. 3, see also fig. 11 for circuit configuration of fig. 10). As such, one would have been motivated to utilize the circuit configuration of fig. 3 expecting the same result of independently controlling each subpixel and driving the display device.
Park and Shigeta ‘500 do not teach an inverter electrically connected between the first node and a second node and that the gate of the second transistor is electrically connected to the second node.
Shigeta ‘080 teaches a similar PWM pixel circuit and further teaches that depending on the type of driving transistor, the signals must be inverted (¶ 113).
The combination of Park, Shigeta ‘500 and Shigeta ‘080, therefore, teaches an inverter electrically connected between the first node and a second node and that the gate of the second transistor is electrically connected to the second node. Park teaches in ¶ 85, that the plurality of transistors may be N-type or P-type transistors and Shigeta ‘080 teaches that an inverter is to be utilized in order to match the control voltage of the driving transistor with its type. For example, by changing DT2 of Park in fig. 3 from an N-type to a P-type, the signal at the gate of the transistor must be inverted.
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Park, Shigeta ‘500 and Shigeta ‘080. The references teach similar PWM driving circuits for pixels and while Park teaches that different types of transistors may be utilized in such circuits, Shigeta ‘080 teaches that the signals must be inverted when changing the type of such transistors. As such, one would have been motivated to make such a combination and add an inverter at the gate of the driving transistor of the PWM circuit in order to properly control the output of the driving transistor and accurately control the light emission of the pixel.
Regarding claim 13, Park does not teach that a first data voltage is applied to the pulse amplitude modulator in the first sub-frame period, and a second data voltage is applied to the pulse amplitude modulator in the second sub-frame period.
Shigeta ‘080, however, teaches that a first data voltage is applied to the pulse amplitude modulator in the first sub-frame period (fig. 14B, see application of Va during activation of Gate(0)), and a second data voltage is applied to the pulse amplitude modulator in the second sub-frame period (fig. 14B, see application of Va during activation of Gate(1); also see ¶ 126).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Park, Shigeta ‘500 and Shigeta ‘080. The references teach addressing each pixel independently and Shigeta ‘080 further teaches writing PAM data information for each corresponding pixel during the writing period for each pixel. As taught by Park in ¶ 5, PAM data expresses gray scale information of a pixel with an amplitude of a pulse, while PWM data expresses gray scale information of a pixel with a width of a pulse. Accordingly, one would have been motivated to combine the teachings in order to include both amplitude and pulse data for each pixel/subpixel, thereby increasing the accuracy of the display device by more accurately expressing the gray scale of each pixel/subpixel.
Claims 7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Park and Shigeta ‘500, as applied above, further in view of Lin et al., US 2025/0111817 A1, hereinafter “Lin”.
Regarding claim 7, Park teaches that the pulse width modulator is electrically connected between the light-emitting element and the pulse amplitude modulator (see fig. 10).
Park and Shigeta ‘500 do not teach that the light-emitting element is electrically connected to a line which transmits a high power voltage, the pulse amplitude modulator is electrically connected to a line which transmits a low power voltage.
Lin, however, teaches that the light-emitting element (fig. 1, L1) is electrically connected to a line which transmits a high power voltage (VDD), the pulse amplitude modulator (fig. 1, PAM) is electrically connected to a line which transmits a low power voltage (VSS).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to modify the teachings of Park, Shigeta ‘500 and Lin. The references teach a pixel circuit including PWM and PAM units and Lin further teaches that the order of connection of such elements may be altered. As such, one would have been motivated to modify the teachings of Park in view of Lin and swap the positions of the LED and the PAM unit (as taught by Lin) which are serially connected and are not affected by a change of position on a line which carries the same current, expecting the same result of driving the pixel unit.
Regarding claim 16, Park teaches that the transistor is electrically connected between the light-emitting element and the pulse amplitude modulator (see fig. 10).
Park and Shigeta ‘500 do not teach that the light-emitting element is electrically connected to a line which transmits a high power voltage, the pulse amplitude modulator is electrically connected to a line which transmits a low power voltage.
Lin, however, teaches that the light-emitting element (fig. 1, L1) is electrically connected to a line which transmits a high power voltage (VDD), the pulse amplitude modulator (fig. 1, PAM) is electrically connected to a line which transmits a low power voltage (VSS).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to modify the teachings of Park, Shigeta ‘500 and Lin. The references teach a pixel circuit including PWM and PAM units and Lin further teaches that the order of connection of such elements may be altered. As such, one would have been motivated to modify the teachings of Park in view of Lin and swap the positions of the LED and the PAM unit (as taught by Lin) which are serially connected and are not affected by a change of position on a line which carries the same current, expecting the same result of driving the pixel unit.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SEPEHR AZARI/ Primary Examiner, Art Unit 2621
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