DETAILED ACTION
This action is responsive to the Response to Election/Restriction filed August 18, 2026. Claims 1-20 are pending. Claims 1, 10 and 16 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Species 1 (claims 1-9 and 16-20) in the reply filed on August 18, 2026, is acknowledged.
Claims 1-9 are generic with regard to species as they read on both Species 1 & 2. They will be examined as they apply to elected Species 1. No pending claim is drawn only to Species 2 but claims that later become directed solely to Species 2 will be withdrawn under 37 CFR 1.142(b).
Claims 16-20, are drawn only to Species 1 and will be examined as such.
Claims 10-15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention (Group II, method), there being no allowable generic or linking claim.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on January 10, 2025. This IDS has been considered.
Claim Objections
Claim 6 is objected to because of the following informalities:
The claim recites “a first voltage drop associated with the first read current and a voltage drop associated with the second read current”. It should read “a second voltage drop associated with the second read current”. Fig. 10 and para. 93 support the change. Appropriate correction is required.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following features must be shown or the feature(s) canceled from the claims:
The claimed structural element “voltage generator” (configured to generate a code value) of claims 1 and 16.
The dummy cell string in the first region of claim 16. Fig. 10 of the instant application depict the connections indicated in claim 16 but not the region assignment. The drawings fail to show a first region that includes both a cell string and a dummy cell string, and a second region that stores the write-voltage and reference resistance values.
OTP as a second region of the memory cell array of claims 9 and 20. No figure depicts OTP as a region of array 110.
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The current title fails for the following reasons:
The withdrawn invention is still referenced in the title (AND METHOD OF OPERATING THE SAME)
WHICH GENERATES OPTIMAL WRITE VOLTAGE – does not track the elected device claims. Additionally, the term ‘optimal’ is promotional, not descriptive.
The following title is suggested: Memory Device Storing a Write Voltage Based on a Reference Resistance.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1–7 and 9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3, 4, 7, 9, and 16 of U.S. Patent No. 12,009,020. Although the claims at issue are not identical, they are not patentably distinct because the claims of the instant application are broader versions of the claims of the '020 patent anticipated by the reference claims as illustrated below.
Independent claim 1 is met by claims 1/16 of U.S. Patent No. 12,009,020 as follows:
#
Instant claim 1
‘020 claims 1 / 16
NSDP rationale
1
A memory device comprising a memory cell array
A memory device comprising a memory cell array including a first memory cell region and a second memory cell region (pat. 1, 16)
Instant 1 is broader (no regions required). Instant 16 recites first and second regions. Broader/same scope is not a distinction. Pat. 1 and 16 already claim the two-region array.
2
a voltage generator configured to generate a code value corresponding to a write voltage
a voltage generator configured to generate a code corresponding to a write voltage (pat. 1); a voltage generator configured to generate a code corresponding to a program voltage (pat. 16)
Same element. “Code value” / “code,” “write voltage” / “program voltage” are the same thing. No distinction.
3
a write driver configured to store data in the memory cell array based on the code value
a write driver configured to store data in the first memory cell region in response to the code (pat. 1); a write driver configured to drive a program current storing data in the selected memory cell in response to the code, and provide the program current … through the bit line (pat. 16)
Same driver function. Instant does not require the current to be identified as going through a bit line; that is extra in the patent, not extra in the instant claims. Instant is broader or coextensive.
4
the device is configured to store a value of the write voltage and use the write voltage to program at least one memory cell
the second memory cell region stores a value defining the write voltage (pat. 1); stores a value defining the program voltage (pat. 16)
Same stored write-voltage value, used to program. Instant 1 does not even require the store to be in a second region (broader). Instant 16 matches pat. 1/16 on where it is stored. “Use … to program” is implicit in a stored write voltage for an MRAM. Not distinct.
5
configured to store a value of a reference resistance and use the reference resistance to distinguish between a parallel state and an anti-parallel state
write voltage determined in relation to a reference resistance distinguishing a parallel state and an anti-parallel state (pat. 1); second region stores another value defining an optimal reference resistance … distinguishing via first/second-state fail-bit counts (pat. 16)
Pat. 1 already uses Rref to distinguish P/AP. Pat. 16 already stores the Rref value in the second region. Instant’s “store Rref and use it to distinguish P/AP” is pat. 16. Instant 1 is an obvious variant of pat. 1 in view of pat. 16 (store the Rref that pat. 1 already uses). Not distinct.
6
the value of the write voltage is based on a value of an initial write voltage corresponding to the value of the reference resistance
the write voltage is determined in relation to a reference resistance … and further in relation to an initial write voltage applied to a magnetic tunnel junction element (pat. 1); the program voltage is determined in relation to the optimal reference resistance and an initial program voltage applied to at least one of the memory cells (pat. 16)
Same first input to the stored voltage: Rref plus an initial write/program voltage. Instant’s “corresponding to the value of the reference resistance” is the same relationship pat. 1/16 already claim (“in relation to”). Not distinct.
7
and a value of a final write voltage obtained based on the value of the initial write voltage
(no separate “final” word in pat. 1 or 16; the claimed write/program voltage is the value determined from Rref + initial V)
Product-by-process on the stored number. Instant still claims a device that stores one write-voltage value derived from Rref and an initial voltage. How that number was refined (a later “final” after the initial) does not change the apparatus. The patented device stores the determined write voltage and uses it. Not a patentable distinction. See MPEP 2113; ODP looks at the claimed product.
The differences are not patentable distinctions.
Instant claim 1 does not require first and second regions. That is broader than patented claims 1 and 16, not narrower.
“Code value” / “code” and “write voltage” / “program voltage” are the same elements.
Storing both the write-voltage value and the reference-resistance value, and using the reference resistance to distinguish parallel from anti-parallel, is patented claim 16.
“The value of the write voltage is based on a value of an initial write voltage corresponding to the value of the reference resistance” is the same relationship patented claims 1 and 16 already recite (“determined in relation to” a reference resistance and an initial write/program voltage).
“And a value of a final write voltage obtained based on the value of the initial write voltage” is a product-by-process recitation of how the stored number was obtained. Instant claim 1 still claims a memory device that stores a write-voltage value derived from a reference resistance and an initial write voltage and uses that value to program a cell. That is the device of patented claims 1 and 16. The intermediate “final” label on the stored number does not add structure. See MPEP § 2113.
Instant claim 1 is therefore a broader or obvious variant of patented claims 1 and 16.
The dependent claims 2-7 and 9 do not add a patentable distinction:
Claim 2. Each memory cell includes a cell transistor with a first end connected to a source line and a gate connected to a word line, and an MTJ with a first end connected to a second end of the cell transistor and a second end connected to a bit line. That is patented claims 2 and 17. Not distinct from patented claim 1 or 16 as limited by those claims.
Claim 3. The value of the final write voltage is based on a program operation using at least one voltage value different from the initial write voltage and on counting fail bits by a read operation. That is how the stored write-voltage value was obtained. Patented claims 1, 10, and 16 already determine the stored write/program voltage from an initial voltage and from fail-bit work associated with the reference resistance. The additional process steps do not add structure to the device and are not a patentable distinction.
Claim 4. The program and read operations of claim 3 are performed in a linear search method or a binary search method. An obvious implementation of the iterative determination already in patented claims 10–12 and 16. Not distinct.
Claim 5. The write driver includes a first type of transistor from a first power supply voltage to an output node and a second type of transistor from a second power supply voltage to the output node, the output node connected to the at least one memory cell. That is patented claims 7 and 19. Not distinct.
Claim 6. A sensing circuit with a first current source, a second current source, and a sense amplifier that amplifies a difference between voltage drops associated with the two read currents, the sensing circuit determining data based on the reference resistance. Patented claim 3 recites the two current sources and the sense amplifier comparing the drop on a selected bit line to the drop on a reference bit line. Patented claim 4 places a resistance equal to the reference resistance on that reference bit line. Instant claim 6 is not distinct from patented claims 1 and 16 as limited by patented claims 3 and 4.
Claim 7. The value of the reference resistance is obtained based on a first fail-bit counting result on cells programmed to the parallel state using a plurality of resistance values and a second fail-bit counting result on cells programmed to the anti-parallel state using those resistance values. That is patented claims 16 and 10–12. Not distinct.
Claim 9. The programmed cell is in a first region of the memory cell array; the write-voltage value and the reference-resistance value are stored in a second region of the memory cell array that includes a one-time programmable memory. Patented claim 1 already puts the stored write-voltage value in a second memory cell region. Patented claim 16 already stores both the program-voltage value and the reference-resistance value in that region. Patented claim 9 recites that the second memory cell region is an anti-fuse cell array. Instant claim 9 is not distinct from patented claims 1, 9, and 16.
Claim Rejections - 35 USC § 112 – Written Description
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1, 9, 16 and 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 1 and 16, each claim recites “a voltage generator configured to generate a code value corresponding to a write voltage”.
That element appears in the abstract, in para. 7 and 9 of the Summary section of the Specification, and in the claims. It does not appear in the detailed description, nor does any figure depict a voltage generator.
What the specification actually describes is control logic circuit 180. Fig. 2 shows circuit 180 as a block of device 100. Para. 54 states that circuit 180 controls write driver 140 so that a program voltage of a desired level is generated. Figs. 21 and 22 show driver 140 receiving digital codes CVU and CVD from circuit 180 and steering write current with those codes. Circuit 180 is not described as a voltage generator. It is not described as generating a code value that corresponds to a write voltage. The codes are simply supplied to the driver.
A person of ordinary skill in the art reading the original disclosure would not understand the inventor to have been in possession of a voltage generator that generates a code value corresponding to a write voltage. Identifying circuit 180 as that generator after the fact is examiner reconstruction, not a description of the claimed element. See MPEP § 2163.02.
The original disclosure also does not describe any other block that performs the claimed generating function. Possession cannot be shown by the claim language alone.
Regarding claims 9 and 20, the claims recite that the second region that stores the value of the write voltage and the value of the reference resistance, and includes a one-time programmable (OTP) memory. The specification does not describe an OTP memory that is a region of the memory cell array.
OTP 115 is described as an additional memory of the device. No embodiment shows the OTP sitting inside array 110 as the second region that stores the two values.
A person of ordinary skill in the art would not have recognized that the inventor was in possession of an OTP memory as a second region of the memory cell array.
Regarding claims 16-20, claim 16 requires a first region that includes a cell string and a dummy cell string, the cell string including MTJ cells, and a second region that stores the write-voltage value and the reference-resistance value.
The original disclosure does not describe that arrangement. Fig. 10 and specification para. 89-91 put the MJT data string in the first region 110a and the dummy string (reference bit line, reference source line, cell transistors, no MTJ) in the second region 110b. Para. 162 again calls 110b the dummy region. Para. 163 stores the two values in OTP memory 115, which para. 55 introduces as a further component of the device, not as region 110b. No embodiment has a dummy cell string in the first region and a different second region that stores those values.
A person of ordinary skill in the art would not have recognized that the inventor was in possession of the claimed first-region dummy string and second-region store. Claims 17-20 depend from claim 16 and do not supply the missing disclosure.
Claim Rejections - 35 USC § 112 – Indefiniteness
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1, 3, and 16-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 1, 3, 16 and 18, claims 1 and 16 recite that “the value of the write voltage is based on a value of an initial write voltage corresponding to the value of the reference resistance and a value of the final write voltage obtained based on the value of the initial write voltage”. The claims already introduce a write voltage, a stored value of that write voltage, an initial write voltage, and a final write voltage. It is unclear which quantity is stored and used to program: the final value, some unspecified combination of the initial and final values, or both. “Corresponding to the value of the reference resistance” is likewise undefined. The specification stores and uses the final/optimal voltage after fine trim (see para. 114 & 163). That does not resolve the claim. Claims 3 and 18 further limit “the value of the final write voltage” and inherit the same ambiguity.
For purposes of examination and application of prior-art, the stored write-voltage value is construed as the final trim result.
Regarding claims 16-20, claim 16 requires a first region that includes a cell string and a dummy cell string, and a second region that stores the write-voltage value and the reference-resistance value. Fig. 10 and specification para 89-91 and 162 assign those roles differently: first region 110a is the MTJ data string, second region 110b is the dummy region (no MJT), and the two values are stored in OTP 115 (as per specification para. 163), which is not region 110b. As written, it is unclear which disclosed structure is the claimed first region, dummy cell string, or second region. Claims 17-20 depend from claim 16 and do not cure the assignment.
Claims 16-20 being rejected under 35 U.S.C. § 112(a) and (b) as set forth above, will not have prior art applied in this action. Claims 17-20 recite limitations corresponding to claims 2-4 and 9 respectively. Those corresponding limitations are unpatentable over Kim in view of Kang for the same reasons as claims 1-4 and 9. If claim 16 is amended to overcome the 112 rejections and is then rejected over the art applied to claim 1, claims 17-20 will be rejected on that same combination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20220336000), in view of Kang (US 20180018134).
Regarding independent claim 1, notwithstanding the rejections for written description and indefiniteness above, Kim discloses a memory device comprising:
a memory cell array (Fig. 2, where it illustrates Memory Cell Array 110);
a voltage generator configured to generate a code value corresponding to a write voltage (Fig. 2, Control Logic Circuit & Voltage Generator 180. See also para. 118; “The voltage generator 182 may generate the code CV controlling the write driver 140”);
and a write driver configured to store data in the memory cell array based on the code value (Fig. 2, Write Driver 140. See also para. 98; “the write driver 140 may perform the pre-program operation on memory cells of the memory device being tested in response to the code CV”. And see para 42; “the write driver 140 may drive a program voltage (or a write current) for storing write data”),
wherein the memory device is configured to store a value of the write voltage and use the write voltage to program at least one memory cell among a plurality of memory cells of the memory cell array (para. 151; “the test device 1200 may store the value of the optimal reference resistance Rref and the value of the optimal write voltage (or current) in the memory device 1100 in the form of a table. For example, the table may be stored in the second region of the memory cell array 110.” And see para. 144; “Then information (e.g., a value) defining (or describing) the optimal write voltage/current may be stored in the memory device (S155)”, “the stored write voltage for the memory device may be used during write operations responsive to end user inputs”),
and is configured to store a value of a reference resistance and use the reference resistance to distinguish between a parallel state and an anti-parallel state of the at least one memory cell (para. 151; “store the value of the optimal reference resistance Rref and the value of the optimal write voltage (or current) in the memory device 1100”. See also para. 72; “a pre-program operation may be performed. Here, the pre-program operation is a specialized, post-fabrication programming operation used to identify (or search for) a value of an optimal reference resistance optimally distinguishing the parallel state from the anti-parallel state.”. Further, see para. 103; “The second read current IRD2 may be used to determine a voltage drop in the reference resistance Rref connected to a second node N2 of the sensing circuit 150 through a reference bit line (Rref BL).”),
and wherein the value of the write voltage is based on a value of an initial write voltage corresponding to the value of the reference resistance (para. 143; “an optimal write voltage/current may be determined that corresponds to the optimal reference resistance and to the initial write voltage (S150)”)
Kim discloses determining and storing a write voltage that corresponds to Rref and to an “initial write voltage”, but is silent with respect to obtaining a later (final) write-voltage value from that initial value.
However, Kang teaches and a value of a final write voltage obtained based on the value of the initial write voltage (Fig. 4. See also para. 5; “writing data to the resistive storage cells using a write current of a set condition; determining whether the writing of data to the resistive storage cells is successful, wherein the writing of data is determined to be failed when the number of resistive storage cells with failed writing of data exceeds a reference value.”. See also para. 20; “The write current generation unit may generate a write current using the optimum condition information stored in the optimum condition storage unit, in order to perform a write operation.”).
Kim and Kang are from the same field of endeavor as applicant’s invention directed to operating an MJT memory array. Kim stores an Rref-tied write voltage and uses it later. Kang iterates that voltage after a fail-bit count and storing the resulting condition for later writes. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply Kang’s fail-bit strengthen/ease loop with Kim’s already stored, Rref-corresponding write voltage so that he stored code used in later writes is the condition that actually passes. Doing so would yield the predictable result of fewer later write fails.
Regarding claim 2, Kim and Kang combined disclose the limitations of claim 1.
As applied, Kim further discloses wherein the at least one memory cell includes:
a cell transistor including a first end connected to a source line and a gate electrode connected to a word line (Fig. 3 where it illustrates memory cell MC1, with a first end connected to source line SL1 and a gate electrode connected to word line WL1).
and a magnetic tunnel junction element including a first end connected to a second end of the cell transistor and a second end connected to a bit line (Fig. 3 where it illustrates the MTJ of MC1 connected to transistor CT and the second end connected to bit line BL1).
Regarding claim 3, Kim and Kang combined disclose the limitations of claim 1.
As applied, Kang further discloses wherein the value of the final write voltage is based on a program operation on the at least one memory cell using at least one voltage value different from the value of the initial write voltage (Fig. 4. See also para. 77; “The write step S410 of the first test cycle may be performed under the condition referred to as an ‘initial condition.’”. Further, see para. 14; “when the set condition is changed, the level of a write voltage applied between the one or more bit lines and the one or more source lines”, “may be adjusted to increase the amount of the write current.”),
and based on counting fail bits among the at least one memory cell by a read operation (para 78; “At the pass/fail determination step S420, the memory circuit may count the number of resistive storage cells among the plurality of resistive storage cells, in which data as desired is not stored. For example, the memory circuit may determine resistive storage cells, in which data as desired is not stored, through a read operation. Hereafter, the counted number of resistive storage cells that have failed in writing desired data will be referred to as the number of fail bits.”).
Regarding claim 4, Kim and Kang combined disclose the limitations of claim 3.
As applied, Kang further discloses wherein the program operation using the at least one voltage value different from the value of the initial write voltage and the read operation are performed in a linear search method or a binary search method (para. 6; “repeating the writing of data, the determining step, the strengthening or easing the set condition.” See also para. 87; “At the condition change step S440, the memory circuit may change a set condition for a write operation of the next test cycle according to the determination result of the pass/fail determination step S420.”, “the memory circuit may strengthen the set condition with regard to the current condition when the write operation was determined as a fail.”. And further see para. 88; “To strengthen the set condition, the amount and pulse width of the write current IW may be controlled as follows: (1) the amount of the write current IW may be increased while the pulse width of the write current IW is maintained. (2) Alternatively, the pulse width of the write current IW may be increased while the amount of the write current IW is maintained. (3) Alternatively, both of the amount and pulse width of the write current IW may be increased. (4) Alternatively, the product of the write current IW and the pulse width may be increased.”. It is noted that under BRI, Kang’s sequential loop reads on “linear search”. It also reads on the instant application’s own misuse of “binary search” at para. 120.
Regarding claim 5, Kim and Kang combined disclose the limitations of claim 1.
As applied, Kim further discloses, wherein the write driver includes:
a first type of transistor including a first end connected to a first power supply voltage and a second end connected to an output node (Fig. 18. See also para. 116; “the write driver 140 may include transistors PU1 to PUp and PD1 to PDp. The transistors PU1 to PUp may be connected between the first bit line BL1 and a first power supply voltage VDD.”. See also para. 119; “in the case where each of the transistors PU1 to PUp is a p-channel metal oxide semiconductor field effect transistor (MOSFET)”);
and a second type of transistor including a first end connected to a second power supply voltage and a second end connected to the output node, and wherein the output node is connected to the at least one memory cell (para. 116; “ The transistors PD1 to PDp may be connected between the first bit line BL1 and a second power supply voltage VSS.”. Further see para. 120; “transistors PD1 to PDp is an n-channel metal oxide semiconductor field effect transistor (MOSFET)”).
Regarding claim 6, Kim and Kang combined disclose the limitations of claim 1.
As applied, Kim further discloses further comprising a sensing circuit configured to determine data stored in the at least one memory cell based on the reference resistance (Fig. 16, sensing circuit 150),
wherein the sensing circuit includes: a first current source configured to generate a first read current (Fig. 16, current source generating IRD1);
a second current source configured to generate a second read current (Fig. 16, current source generating IRD2);
and a sense amplifier configured to amplify a difference between a first voltage drop associated with the first read current and a voltage drop associated with the second read current (Fig. 16, Sense Amplifier 152).
Regarding claim 6, Kim and Kang combined disclose the limitations of claim 1.
Regarding claim 7, Kim and Kang combined disclose the limitations of claim 1.
As applied, Kim further discloses wherein the value of the reference resistance is obtained based on:
a first counting result obtained by performing a fail bit counting operation on the plurality of memory cells programmed to the parallel state using a plurality of resistance values with different values (para. 136; “A first program operation may be performed on memory cells of a memory device (S105). For example, a competent test device may program the memory cells to have the resistance distribution Rp of the parallel state”. And see para. 137; “A first fail bit counting may then be iteratively performed for the memory cells of the memory device (S110) in relation to a plurality of reference resistances”, “the test device may count the number of fail bits for the memory cells while incrementally varying the reference resistance Rref.”. Further, see para. 138; “the test device may count the number of fail bits of memory cells while varying the reference resistance Rref in relation to the plurality of reference resistances Rref”, “the first fail bit counting result associated with the parallel state”);
and a second counting result obtained by performing the fail bit counting operation on the plurality of memory cells programmed to the anti-parallel state using the plurality of resistance values (para 139; “the test device may program the memory cells of the memory device to have the resistance distribution Rap of the anti-parallel state”. See also para. 140; “A second fail bit counting may be iteratively performed for the memory cells (S130) in order to generate a second counting result.”, “the test device may count the number of fail bits for the memory cells while varying a value of the reference resistance Rref.”).
Regarding claim 9, Kim and Kang combined disclose the limitations of claim 1.
As applied, Kim further discloses wherein the at least one memory cell is in a first region of the memory cell array (para. 148; ”the command CMD may include a command for programming the first region of the memory cell array 1100 to a specific program state”),
and wherein the value of the write voltage and the value of the reference resistance are stored in a second region of the memory cell array (para. 151; “the test device 1200 may store the value of the optimal reference resistance Rref and the value of the optimal write voltage (or current) in the memory device 1100 in the form of a table. For example, the table may be stored in the second region of the memory cell array 110”),
the second region including a one-time programmable (OTP) memory (Fig. 22. See also para. 151; “the second region may include an anti-fuse cell array.”. And see para 46; “An anti-fuse may be a nonvolatile, one-time programmable (OTP) memory”).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20220336000), in view of Kang (US 20180018134), and further in view of Seo et al. (US 20170062032; “Seo”).
Regarding claim 8, Kim and Kang disclose the limitations of claim 7.
Kim and Kang combined disclose a stored Rref value obtained from P/AP fail-bit counts but are silent with respect to that Rref being a circuit of transistors.
However, Seo teaches wherein the reference resistance comprises a resistance of a circuit comprising:
a plurality of transistors (Fig. 10 where it illustrates reference resistor circuit 116);
and a plurality of resistance elements respectively corresponding to the plurality of transistors, each of the plurality of resistance elements connected between opposite ends of the corresponding one of the plurality of transistors (Fig. 10. See also para 10; “The reference resistor circuit may include a plurality of transistors, which may be connected in parallel to the resistors, respectively. The transistors may be configured to selectively short the resistors in response to respective trimming signals”).
Kim and Kang combined, along with Seo are from the same field of endeavor as applicant's invention directed to operating an MRAM/Resistive memory array. Kim stores a selectable Rref used to distinguish P/AP. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement Kim’s’ stored Rref with Seo’s Fig. 10 network. Doing so would be a predictable way to store the Rref code actually selects the resistance.
Claims 1-9 are rejected under 35 U.S.C. § 103 as set forth above. Claims 16-20 are not rejected under 35 U.S.C. § 102 or § 103 in this action in view of the 112(a) and 112(b) rejections of those claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chih et al. (US20130265820) – MRAM dummy addressing network without MJT used to offset bit-line path resistance into the sense amplifier comparison.
Tanizaki et al. (US 20030189853) – MRAM dummy cell with a series dummy resistance adding portion on the reference data line into a differential sense amplifier.
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/James S. Wells/Examiner, Art Unit 2825
/Alfredo Bermudez Lozada/Primary Examiner, Art Unit 2825
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