DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Claims 1 to 21 are presented for examination. The preliminary amendment filed 417-2025 canceled claim 1 and added new claims 2 to 21.
Information Disclosure Statement
The references listed in the information disclosure statement submitted on 1-10-2025 have been considered by the examiner (see attached PTO-1449).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2 to 8 and 16 to 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the phrase “a plurality of error-detection values” on line 6. It is vague and unclear since the claim refers to a first error-detection information, second error detection information and third error detection information. It is unclear how the phrase “plurality of error-detection values” relates to the (first, second and third) error detection information. Please consider revising.
Independent claim 16 is similar to claim 2 and is also rejected for the same rationale applied to claim 2.
Dependent claims 3 to 8 and 17 to 21 are also rejected due to their dependency on a rejected base claim.
Allowable Subject Matter
Claims 9 to 15 are allowed.
Claims would be allowable once the 35 U.S.C. 112 (b) rejection is overcome.
The following is a statement of reasons for the indication of allowable subject matter: the prior art made of record, teaches numerous methodologies for writing to a memory core and detecting errors using multiple error detection codes. Kanai et al. (USPAP 2007/0124557) discloses a method, an apparatus and a system for protecting memory, the apparatus comprising: a processor, a memory and a memory protecting apparatus coupled to each other. Kanai teaches that the memory protecting apparatus includes a parity generator that generates a parity for first data to be written to the memory and a parity adder that obtains a second data by adding the parity to the first data. Kanai teaches that an access-key register holds an access key unique to a source of request for writing data to the memory. Kanai teaches that a first operating unit that obtains a third data by calculating an XOR between the second data and the access key. Kanai teaches that the memory includes an error correction code and a second XOR circuit calculates an XOR data in the memory and the access key retained in the access-key register. Kanai teaches that the process of reading and writing the data to the memory includes writing the data D and parity added data D’. Kani teaches that a syndrome calculating circuit calculates the syndrome using the ECC when the value of the syndrome is zero, i.e. when no error is detected. Kanai teaches that when the value of syndrome is not zero, the number of bits indicative of one in the syndrome is odd, and the value of the syndrome is equal to any row in the parity check matrix, the error correcting circuit corrects the error and the corrected data is read.
However, the prior art made of record, taken alone or in combination fails to teach or fairly suggest or render obvious the combination of elements with the novel element of the instant invention of: “a controller, comprising: error-detection circuitry coupled to receive first error-detection information from interface circuitry and receive second error-detection information from encoder circuitry, the first error-detection information received, from a memory device and via the interface circuitry, in association with first data; the encoder circuitry to receive the first data and generate the second error- detection information, the second error-detection information to be provided, by the encoder circuitry, to the error-detection circuitry to determine, based on a comparison of the first error-detection information and the second error-detection information.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nagai (USPAP 2005/0210361) teaches an encoding method and encoding apparatus.
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/Shelly A Chase/ Primary Examiner, Art Unit 2112
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