DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
2. The information disclosure statement (IDS) submitted on 01/23/26 has been considered by the examiner.
Specification
3. The disclosure is objected to because of the following informalities: on line 4 of paragraph [0050], --a-- should be inserted after the word “use”, similar to the amendment made by applicant in the response filed on 12/13/18 in parent case 15/939,144. On line 2 of paragraph [0083], “8C” should be changed to --8B--, similar to the amendment made by applicant in the response filed on 12/13/18 in parent case 15/939,144. On line 2 of paragraph [0088], “8C” should again be changed to --8B--, similar to the amendment made by applicant in the response filed on 12/13/18 in parent case 15/939,144.
Appropriate correction is required.
Claim Objections
4. Claims 21, 31 and 37 are objected to because of the following informalities:
On line 7 of claim 21, "a gate of each transistor of" should be changed to --gates of--.
On line 12 of claim 21, "a body of each transistor of" should be changed to
--bodies of--.
On line 7 of claim 31, "a gate of each transistor of" should again be changed to
--gates of--.
On line 16 of claim 31, "a body of each transistor of" should again be changed to
--bodies of--.
On lines 5-6 of claim 37, "a gate of each transistor of" should again be changed to --gates of--.
On lines 9-10 of claim 37, "a body of each transistor of" should again be changed to --bodies of--.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
5. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 21-40 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
On lines 12-13 of claim 21, "a respective pair of transistors among the plurality of transistors" lacks clear antecedent basis, the reason being that "a respective pair of transistors among the plurality of transistors" has already been recited on lines 7-8 of claim 21, i.e., it cannot be determined whether or not these two recitations are referring to the same respective pair of transistors among the plurality of transistors. If so, "a respective pair" on line 12 of claim 21 should be changed to --the respective pair--. Otherwise, "a respective pair" recited on line 7 should be changed to --a first respective pair--, and "a respective pair" recited on line 12 should be changed to --a second respective pair--.
On lines 4-5 of claim 27, "a respective pair of adjacent transistors of the plurality of transistors" also lacks clear antecedent basis, the reason being that "a respective pair of adjacent transistors of the plurality of transistors" has already been recited on lines 2-3 of claim 27, i.e., cannot be determined whether or not these two recitations are referring to the same respective pair of adjacent transistors. If so, "a respective pair" on the last line of claim 27 should be changed to --the respective pair--. Otherwise, "a respective pair" recited on lines 2-3 of claim 27 should be changed to --a first respective pair--, and "a respective pair" recited on the last two lines of claim 27 should be changed to --a second respective pair--.
On lines 16-17 of claim 31, "a respective pair of transistors among the plurality of transistors" also lacks clear antecedent basis, the reason being that "a respective pair of transistors among the plurality of transistors" has already been recited on lines 7-8, i.e., it cannot be determined whether or not these two recitations are referring to the same respective pair of transistors. If so, "a respective pair" recited on line 16 of claim 31 should be changed to --the respective pair--. Otherwise, "a respective pair" recited on line 7 of claim 31 should be changed to --a first respective pair--, and "a respective pair" recited on line 16 of claim 31 should be changed to --a second respective pair--.
On lines 4-5 of claim 35, "a respective pair of adjacent transistors of the plurality of transistors" also lacks clear antecedent basis, the reason being that "a respective pair of adjacent transistors of the plurality of transistors" has already been recited on lines 2-3 of claim 35, i.e., it cannot be determined whether or not these two recitations are referring to the same respective pair of adjacent transistors. If so, "a respective pair" recited on the last two lines of claim 35 should be changed to --the respective pair--. Otherwise, "a respective pair" recited on lines 2-3 of claim 35 should be changed to --a first respective pair--, and "a respective pair" recited on the last two lines of claim 35 should be changed to --a second respective pair--.
On line 10 of claim 37, "a respective pair of transistors among the plurality of transistors" also lacks clear antecedent basis, the reason being that "a respective pair of transistors among the plurality of transistors" has already been recited on line 6 of claim 37, i.e., it cannot be determined whether or not these two recitations are referring to the same respective pair of transistors. If so, "a respective pair of transistors" on line 10 of claim 37 should be changed to --the respective pair of transistors--. Otherwise, "a respective pair of transistors" recited on line 6 of claim 37 should be changed to --a first respective pair of transistors--, and "a respective pair of transistors" recited on line 10 of claim 37 should be changed to --a second respective pair of transistors--.
Claims 22-26, 28-30, 32-34, 36 and 38-40 are rejected as being indefinite in view of their dependencies, directly or indirectly, on the above-noted indefinite claims 21, 27, 31, 35 and 37.
Claim Rejections - 35 USC § 102
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 21-40 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kerr et al, U.S. Patent No. 10,320,379.
As to claim 21, Kerr et al discloses, in figure 2,
a transistor switch stack (the claimed transistor switch stack reads on all of the circuitry shown in Kerr et al’s figure 2) comprising:
a first terminal (the claimed first terminal reads on the terminal which receives signal RF1 in Kerr et al's figure 2);
a second terminal (the claimed second terminal reads on the terminal which outputs signal RF2 in Kerr et al's figure 2);
a plurality of transistors (the claimed plurality of transistors read on transistors Q1 through QN shown in Kerr et al's figure 2) coupled between the first terminal and the second terminal, wherein each transistor is coupled to at least one other transistor of the plurality of transistors;
a first plurality of resistors (the claimed first plurality of resistors read on the seven resistors RG to the right of resistor RG1 shown in Kerr et al's figure 2), wherein each resistor of the plurality of resistors is coupled between gates of a respective pair of transistors among the plurality of transistors;
a first capacitor (the claimed first capacitor reads on capacitor CG1 shown in Kerr et al's figure 2) coupled between the first terminal and a first resistor (the claimed first resistor can be read on any one of the above-noted seven resistors RG shown in Kerr et al's figure 2) of the first plurality of resistors;
a second plurality of resistors (the claimed second plurality of resistors read on the seven resistors RB to the right of resistor RB1 shown in Kerr et al's figure 2), wherein each resistor of the second plurality of resistors is coupled between bodies of a respective pair of transistors among the plurality of transistors; and
a second capacitor (the claimed second capacitor reads on capacitor CB1 shown in Kerr et al's figure 2) coupled between the first terminal and a first resistor (the claimed first resistor can be read on any one of the above-noted seven resistors RB shown in Kerr et al's figure 2) of the second plurality of resistors.
As to claim 22, the claimed first transistor can be read on Kerr et al's transistor Q1 and the claimed second transistor can be read on Kerr et al's transistor QN.
As to claim 23, the claimed second resistor can be read on either resistor RG1 or resistor RGC1 shown in Kerr et al's figure 2 (note that resistor RG1 is directly coupled to the above-noted first resistor of the first plurality of resistors and resistor RGC1 is indirectly coupled to the above-noted first resistor of the first plurality of resistors, i.e., coupled thereto via resistor RG1), and the claimed third resistor can be read on either resistor RB1 or resistor RBC1 shown in Kerr et al's figure 2 (note that resistor RB1 is directly coupled to the above-noted first resistor of the second plurality of resistors and resistor RBC1 is indirectly coupled to the above-noted first resistor of the second plurality of resistors, i.e., coupled thereto via resistor RB1).
As to claim 24, note that Kerr et al's first plurality of resistors form a gate bias resistor ladder with a first end (the first end is the node between resistor RG1 and the resistor RG adjacent to it) coupled to the second resistor (the second resistor is resistor RG1), and a second end (the second end is the node between any other resistors RG) configured to receive a gate bias voltage (note that each of the nodes between resistors RG inherently receives a gate bias voltage, i.e., the gate bias voltage imparted by bias voltage GATE CONTROL as it is transmitted from terminal 22 to resistor RGN).
As to claim 25, note that Kerr et al's second plurality of resistors form a body charge control resistor ladder with a first end (the first end is the node between resistor RB1 and the resistor RB adjacent to it) coupled to the third resistor (the third resistor is resistor RB1), and a second end (the second end is the node between any other resistors RB) configured to receive a body bias voltage (note that each of the nodes between resistors RB inherently receives a body bias voltage, i.e., the body bias voltage imparted by bias voltage BODY CONTROL as it is transmitted from terminal 34 to resistor RBN).
As to claim 26, the claimed one or more transistors coupled between the first transistor and the second transistor can be read on Kerr et al's transistors Q2 through Q7.
As to claim 27, note that each resistor of the above-noted first plurality of resistors in Kerr et al's figure 2 is coupled between the gates of a respective pair of adjacent transistors of the plurality of transistors, and note further that each resistor of the above-noted second plurality of resistors is coupled between the bodies of a respective pair of adjacent transistors of the plurality of transistors.
As to claim 28, note that Kerr et al's signal RF1 is configured to be coupled to a radio frequency voltage source, and note further that each of transistors Q1 through QN can be interpreted as a positive-logic field-effect transistor, the reason being that each of these transistors is an NMOS field-effect transistor which turns on in response to a positive logic level input signal at its gate terminal.
As to claim 29, the claimed third plurality of resistors can be read on the resistors RSD shown in figure 2 of Kerr et al, note that each of these resistors is coupled between a drain and source of a respective transistor of the claimed plurality of transistors, and note further that these resistors form a drain-source bias resistor ladder having a first end coupled to the above-noted first terminal and a second end coupled to the above-noted second terminal.
As to claim 30, all of the limitations of this method claim will be inherent during the operation of Kerr et al's figure 2 transistor switch stack, note that Kerr et al's transistors Q1 through QN will inherently be biased through voltage division of a first bias voltage (bias voltage GATE CONTROL) based on the above-noted first plurality of resistors and the above-noted first capacitor, radio frequency signal RF1 will inherently be selectively provided from the above-noted first terminal to the above-noted second terminal based on the biasing provided by bias voltage GATE CONTROL, and the body charge associated with the plurality of transistors Q1 through QN will inherently be controlled through voltage division of second bias voltage BODY CONTROL based on the above-noted second plurality of resistors and the above-noted second capacitor.
As to claims 31-40, all of the limitations of these method claims will similarly be inherent during the operation of Kerr et al's figure 2 transistor switch stack, similar to the above-noted discussion of method claim 30.
Prior Art Not Relied Upon
7. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Figure 2 of Granger-Jones et al (USPAP 2011/0260774) is also seen to anticipate all of the limitations of claims 21-40, note that the claimed first and second terminals can be read on terminals 40 and 46, respectively, the claimed plurality of transistors coupled between the first terminal and the second terminal can be read on transistors Q1 through Q5, the claimed first plurality of resistors can be read on resistors Rg, the claimed second plurality of resistors can be read on resistors Rb, the claimed first capacitor can be read on capacitor 66, and the claimed second capacitor can be read on capacitor 72.
Figures 29 and 38 of Altunkilic et al (USPAP 2014/0009214), when combined, provide a transistor switch stack which anticipates all of the limitations of claims 21-40, note that the claimed first and second terminals can be read on terminals 144 and 146, respectively, shown in figure 29 (or terminals P1 and P2 shown in figure 38), the claimed plurality of transistors can be read on transistors M1 through MN in figure 29 (or transistors FET1 through FET5 in figure 38), the claimed first plurality of resistors can be read on resistors Rgg1 through Rgg (N-1) in figure 29 (or resistors Rg1 through Rg5 in figure 38), the claimed second plurality of resistors can be read on resistors Rb in figure 29 (or resistors Rb1 through Rb5 in figure 38), the claimed first capacitor can be read on capacitor Cfwd shown in figure 29, and the claimed second capacitor can be read on capacitor Cfwd shown in figure 38. Applicant also note figures 12E and 12F of Altunkilic which suggests that the embodiments illustrated in figures 29 and 38 of this reference can be combined into a single embodiment.
Figure 7 of Heaney et al (USPAP 2013/0009725) is also seen to anticipate all of the limitations of claims 21-40, note that this reference also shows a transistor switch stack comprising the claimed first and second terminals (the terminals at the top and bottom center of figure 7), the claimed plurality of transistors coupled between the first and second terminals (the three field effect transistors at the center of figure 7), the claimed first plurality of resistors (gate resistors 61), the claimed second plurality of resistors (body resistors Rbias), the claimed first capacitor (capacitor Ccoupling), and the claimed second capacitor (the capacitor to the right of capacitor Ccoupling).
Conclusion
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH B WELLS whose telephone number is (571)272-1757. The examiner can normally be reached Monday-Friday, 8:30am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, REGIS BETSCH, can be reached at (571)270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNETH B WELLS/Primary Examiner, Art Unit 2842 June 1, 2026
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