DETAILED ACTION
Status of Claims
Claims 1 – 20 are pending.
Claims 1, 10, and 16 are independent.
This office action is Non-Final.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 2, 4,9, 10,14 and 16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3, 4, 6, 9,15 and 17 of U.S. Patent No. 12,228,962. Although the claims at issue are not identical, they are not patentably distinct from each other because they are directed to the same invention; a clock skew calibration circuit configured to be coupled to a multi-phase clock generator through a plurality of delay lines, wherein a first clock skew calibration unit comprises a frequency doubler configured to receive a plurality of multi-phase clock signals and generate a clock signal based on the plurality of multi-phase clock signals, a frequency divider configured to receive the clock signal and generate a reduced frequency signal based on the clock signal, and a delay line control circuit configured to compare the duty cycle of the reduced frequency signal with a predetermined duty cycle. Similarities have been provided in the table below (emphasis added by the Examiner).
Instant Application No. ‘409
Patent No. ‘962
1. An apparatus comprising: a clock skew calibration circuit configured to be coupled to a multi-phase clock generator through a plurality of delay lines, wherein a first clock skew calibration unit of the clock skew calibration circuit comprises: a frequency doubler configured to receive a plurality of multi-phase clock signals and generate a clock signal; a frequency divider configured to receive the clock signal and generate a reduced frequency signal indicative of a skew of a first multi-phase clock signal; and a delay line control circuit configured to adjust the skew of the first multi-phase clock signal by comparing the reduced frequency signal with a predetermined duty cycle, and generating a control signal to modify a delay applied to the first multi-phase clock signal.
1. An apparatus comprising: a clock skew calibration circuit configured to be coupled to a multi-phase clock generator through a plurality of delay lines, wherein a first clock skew calibration unit of the clock skew calibration circuit comprises: a frequency doubler configured to receive a plurality of multi-phase clock signals and generate a clock signal based on the plurality of multi-phase clock signals; a frequency divider configured to receive the clock signal and generate a reduced frequency signal based on the clock signal, the reduced frequency signal having a duty cycle indicating a skew of a first multi-phase clock signal; and a delay line control circuit configured to compare the duty cycle of the reduced frequency signal with a predetermined duty cycle, and generate a first control signal to adjust the skew of the first multi-phase clock signal through adjusting a first delay applied to the first multi-phase clock signal until a calibrated signal of the first multi-phase clock signal is achieved.
2. The apparatus of claim 1, wherein: the multi-phase clock generator is configured to generate four phase clock signals including a 0-degree clock signal, a 90-degree clock signal, a 180-degree clock signal, and a 270-degree clock signal.
4. The apparatus of claim 3, wherein: the multi-phase clock generator is configured to generate 4-phase clock signals comprising a 0-degree clock signal, a 90-degree clock signal, a 180-degree clock signal and a 270-degree clock signal, and wherein: the reference multi-phase clock signal is the 0-degree clock signal; the first multi-phase clock signal is the 180-degree clock signal; the second multi-phase clock signal is the 90-degree clock signal; and the third multi-phase clock signal is the 270-degree clock signal.
4. The apparatus of claim 3, further comprising: a latch circuit configured to receive the reduced frequency signal and generate a direction control signal; and a filter configured to convert the reduced frequency signal into a dc signal indicative of a duty cycle of the reduced frequency signal.
6. The apparatus of claim 1, wherein the first clock skew calibration unit further comprises: a latch circuit configured to generate a direction control signal; and a filter configured to receive the reduced frequency signal and generate a dc signal, wherein a voltage of the dc signal is proportional to the duty cycle of the reduced frequency signal.
9. The apparatus of claim 1, wherein: a second clock skew calibration unit of the clock skew calibration circuit comprises: a first AND gate configured to receive a calibrated signal of the first multi-phase clock signal and a second multi-phase clock signal; a second AND gate configured to receive a reference multi-phase clock signal and the second multi-phase clock signal; and a first comparator configured to compare an output of the first AND gate with an output of the second AND gate, and generate a second control signal to adjust a skew of the second multi-phase clock signal through modifying a delay applied to the second multi-phase clock signal; and. a third clock skew calibration unit of the clock skew calibration circuit comprises: a third AND gate configured to receive the calibrated signal of the first multi-phase clock signal and a third multi-phase clock signal; a fourth AND gate configured to receive the reference multi-phase clock signal and the third multi-phase clock signal; and a second comparator configured to compare an output of the third AND gate with an output of the fourth AND gate, and generate a third control signal to adjust a skew of the third multi-phase clock signal through modifying a delay applied to the third multi-phase clock signal.
3. The apparatus of claim 2, wherein a third clock skew calibration unit of the clock skew calibration circuit comprises: a third logic gate configured to perform a third AND operation on the calibrated signal of the first multi-phase clock signal and a third multi-phase clock signal; a fourth logic gate configured to perform a fourth AND operation on the reference multi-phase clock signal and the third multi-phase clock signal; and a second comparator configured to compare an output of the third logic gate with an output of the fourth logic gate, and generate a third control signal to adjust a skew of the third multi-phase clock signal through adjusting a third delay applied to the third multi-phase clock signal until a calibrated signal of the third multi-phase clock signal is achieved.
10. A method comprising: generating, by a frequency doubler, a clock signal based on a plurality of multi-phase clock signals; generating, by a frequency divider, a reduced frequency signal indicative of a skew of a first multi-phase clock signal of the plurality of multi-phase clock signals; comparing the reduced frequency signal with a predetermined duty cycle; and adjusting the skew of the first multi-phase clock signal by generating a control signal to modify a delay applied to the first multi-phase clock signal.
9. A method comprising: generating, by a frequency doubler, a clock signal based on a plurality of multi-phase clock signals; generating, by a frequency divider, a reduced frequency signal based on the clock signal, the reduced frequency signal having a duty cycle indicating a skew of a first multi-phase clock signal; comparing the duty cycle of the reduced frequency signal with a predetermined duty cycle; and generating, by a delay line control circuit, a first control signal to adjust the skew of the first multi-phase clock signal through adjusting a first delay applied to the first multi-phase clock signal until a calibrated signal of the first multi-phase clock signal is achieved.
14. The method of claim 10, further comprising: converting the reduced frequency signal into a dc signal indicative of a duty cycle of the reduced frequency signal; and generating the control signal based on a comparison between a reference voltage and the dc signal.
15. The method of claim 9, further comprising: converting the reduced frequency signal into a dc signal, wherein a voltage of the dc signal is proportional to the duty cycle of the reduced frequency signal; and comparing the voltage of the dc signal with a reference voltage proportional to the predetermined duty cycle to obtain the first control signal
16. A system comprising: a multi-phase clock generator configured to generate a plurality of multi-phase clock signals; a plurality of delay lines configured to receive the plurality of multi-phase clock signals; and a clock skew calibration circuit coupled to the multi-phase clock generator through the plurality of delay lines, wherein a first clock skew calibration unit of the clock skew calibration circuit comprises a frequency doubler, a frequency divider and a delay line control circuit configured to adjust a skew of a first multi-phase clock signal by modifying a delay applied to the first multi-phase clock signal based on a duty cycle comparison.
17. A system comprising: a multi-phase clock generator configured to generate a plurality of multi-phase clock signals; a plurality of delay lines configured to receive respective multi-phase clock signals; and a clock skew calibration circuit configured to be coupled to the multi-phase clock generator through the plurality of delay lines, wherein of the clock skew calibration circuit comprises a first clock skew calibration unit, a second clock skew calibration unit and a third clock skew calibration unit, and wherein the first clock skew calibration unit comprises: a frequency doubler configured to receive the plurality of multi-phase clock signals and generate a clock signal based on the plurality of multi-phase clock signals; a frequency divider configured to receive the clock signal and generate a reduced frequency signal based on the clock signal, the reduced frequency signal having a duty cycle indicating a skew of a first multi-phase clock signal; and a delay line control circuit configured to compare the duty cycle of the reduced frequency signal with a predetermined duty cycle, and generate a first control signal to adjust a first delay applied to the first multi-phase clock signal until a calibrated signal of the first multi-phase clock signal is achieved.
Appropriate action is required.
Allowable Subject Matter
Claims 3 - 8, 11 – 13, 15, 17 -20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wilhite; Jeffrey B. (US Patent Application Publication No. 2009/0003482 A1) “Broadband Self Adjusting Quadrature Signal Generator And Method Thereof” is cited to teach low noise phase quadrature signals that are generated after receiving a clock signal and adjusting the clock signal in response to a feedback signal to generate a phase adjusted clock signal. The clock signal and the phase adjusted clock signal are exclusive-ORed to generate a frequency doubled signal. An in-phase local oscillator signal and a quadrature local oscillator signal are generated from the frequency doubled signal such that the in-phase local oscillator and the quadrature local oscillator signal are out-of-phase with each other. In addition, a phase relationship between the in-phase local oscillator signal and the quadrature local oscillator signal are detected, and the feedback signal is generated based upon the phase relationship between the in-phase local oscillator signal and the quadrature local oscillator signal.
Mosalikanti; Praveen et al. (US Patent Application Publication No. 2011/0148498 A1) “Digital Quadrature Phase Correction” is cited to teach methods and systems to adjust a phase difference between signals, such as to perform quadrature phase correction. First and second signals are digitally compared, such as with exclusive OR circuitry, to provide a comparison signal having a duty cycle representative of a phase difference between the signals. A phase delay of one or both of the first and second signals is adjusted until the duty cycle of the comparison signal corresponds to a desired phase difference. In a clock and data recovery system, the signals may correspond to a zero degree phase of a first phase interpolator and a ninety degree phase of a second phase interpolator, and digital codes to the first and second phase interpolators may be adjusted to provide a fifty percent duty cycle in the comparison signal.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERRELL S JOHNSON whose telephone number is (571)270-3485. The examiner can normally be reached 10AM-7PM EST M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at 571-270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TERRELL S JOHNSON/Primary Examiner, Art Unit 2176
Prosecution Insights