Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
1. Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 16/010,813, filed on December 24th, 2018.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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2. Claims 1-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-6 of U.S. Patent No. 10,860,370, claims 1-19 of U.S. Patent No. 11,500,677, and claims 1-19 of U.S. Patent No. 12,229,593. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application would be anticipated by those of ‘370, ‘677, and ‘593.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1-19 are rejected under 35 U.S.C. 103 as being unpatentable over Diamos et al (US 2016/0019066, cited in the IDS dated January 1st, 2025, herein Diamos), in view of Blumrich et al (US 2009/0006672, cited in the IDS dated January 1st, 2025, herein Blumrich).
In the following rejections, the processor embodiment of claim 13 will be addressed first.
Regarding claim 13, Diamos teaches a processor comprising:
a scheduling module ([0037], [0051]) comprising:
one or more queues arranged to store scheduled tasks ([0037], [0051]); and
hardware logic arranged, in response to receiving an instruction from an instruction decoder decoding a synchronization instruction in a scheduled task from a group of tasks, to place the scheduled task into a non-active state wherein no instructions in the scheduled task are executed except for the synchronization instruction ([0024], [0064], [0068], convergence barrier, WAIT instruction causes state of threads to be blocked when executed).
Diamos fails to teach wherein the decoded synchronization instruction causes an ALU to perform a check on data assigned to the group of tasks.
Blumrich teaches a processor comprising hardware logic wherein a decoded synchronization instruction causes an ALU to perform a check on data assigned to the group of tasks ([0013], [0038], synchronization operation, [0058-0062], performing memory synchronization operations in response to the sync instruction and tracking of completion condition for data in the task group).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Diamos and Blumrich in order to utilize a synchronization instruction that performs operations on the task data. While Diamos discloses a sync (wait) instruction that specifies a matching barrier, Diamos does not explicitly disclose a single instruction which performs an operation on the data then removes the scheduled tasks from the non-active state. However, Blumrich discloses a sync operation which performs tagging and tracking of task data in order to implement a synchronization barrier, and as both Diamos and Blumrich disclose the use of synchronization operations to perform parallel processor operations, the combination would merely entail a simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Regarding claim 14, The combination of Diamos and Blumrich teaches the processor according to claim 13, wherein the scheduling module further comprises hardware logic arranged, in response to receiving a message from an ALU indicating that the data assigned to the group of tasks passed a check on data assigned to the group of tasks, to remove all scheduled tasks in the group from the non-active state (Diamos [0026], execution unit, [0029], [0062], [0069], clear blocked state when all threads reach convergence barrier).
Regarding claim 15, The combination of Diamos and Blumrich teaches the processor according to claim 13, wherein the scheduling module further comprises hardware logic arranged, in response to receiving a message from an ALU indicating that the data assigned to the group of tasks has failed a check, to leave the scheduled task in the non-active state (Diamos [0064], [0068], threads that reach barrier wait for all tasks in group to reach barrier).
Regarding claim 16, The combination of Diamos and Blumrich teaches the processor according to claim 13, wherein the scheduling module further comprises hardware logic arranged to, dependent upon an outcome of the check, either remove all scheduled tasks in the group from the non-active state or leave the scheduled task in the non-active state (Diamos [0024-0026], [0064-0068], threads wait for all tasks in group to arrive at barrier and become active again once all tasks have reached barrier).
Regarding claim 17, The combination of Diamos and Blumrich teaches the processor according to claim 13, wherein the ALU is an atomic ALU (Diamos [0033], general processing cluster of PPU).
Regarding claim 18, The combination of Diamos and Blumrich teaches the processor according to claim 13, further comprising:
a processing block comprising an atomic ALU arranged to perform an operation on data assigned to the group of tasks and to perform a check on the updated data assigned to the group of tasks, and in response to the updated data passing the check, to send a message from the ALU to the scheduling module indicating that the data assigned to the group of tasks passed the check (Diamos [0051], [0054], [0068], execution unit reports to scheduler when WAIT instruction with corresponding group ID is reached).
Regarding claim 19, The combination of Diamos and Blumrich teaches the processor according to claim 18, wherein the ALU is further arranged, in response to the updated data passing the check, to reset the data assigned to the group of tasks (Diamos [0068], reset blocked state).
Claims 1-7 refer to a method embodiment of the processor embodiment of claims 13-19. Therefore, the above rejections for claims 13-19 are applicable to claims 1-7.
Claims 8-12 refer to a scheduling module embodiment included within the processor embodiment of claims 13-17. Therefore, the above rejections for claims 13-17 are applicable to claims 8-12.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hall (US 2011/0283095) discloses a processor that enforces thread synchronization by using an ALU to block younger instructions from execution.
Yoshida (US 2010/0106945) discloses a processor with a circuit configured to perform a check on a thread subject to a synchronization instruction.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J METZGER whose telephone number is (571)272-3105. The examiner can normally be reached Monday-Friday 8:30-5.
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/MICHAEL J METZGER/ Primary Examiner, Art Unit 2183
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