DETAIL ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. The instant application having application No. 19/017,952 has a total of 20 claims
pending in the application; there are 3 independent claim and 17 dependent claims, all of which are ready for examination by the examiner.
IFORMATION CONCENING DRAWING:
3. Application's drawing submitted on 10/16/2023 are acceptable for examination
purposes.
ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
Information Disclosure Statement
4. As required by M.P.E.P. 2001.06(b) and 37 C.F.R. 1.98(d), since the instant
application has been identified as a continuation application of an earlier filed
application and is relied upon for an earlier filing date under 35 U.S.C. 120, the
examiner has reviewed the prior art cited in the earlier related application as required by M.P.E.P. 707.05 and 904 and as stated in M.P.E.P. 2001.06(b), no separate citation of the same prior art need be made by the applicants in the instant application.
IFORMATION CONCENING IDS:
5. The information disclosure statement (IDS) submitted on 01/13/2025 is in
compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure
statement has been considered by the Examiner. A copy (copies) of PTOL-1449s initialed and signed by the examiner is/are attached to the instant office action.
RELEVANT PRIOR ART CITED BY THE EXAMINER:
6. The following prior art made of record and not relied upon is cited to establish the
level of skill in the applicant's art and those arts considered reasonably pertinent to
applicant's disclosure.
GARG et al. (US 2019/0058731 A1) teaches "… entries in the ARP cache may be determined based on an examination of the shadow ARP cache. In other words, an attempt to overwrite the IP address to MAC address mapping related to the gateway device in the ARP cache of the user device can be detected based on the examination of the shadow ARP cache…” (par. 0033).
ABDALLAH et al. (US 2014/0281242 A1) teaches"… shadow cache stores
copies of cache lines that are stored at the target addresses of first far taken
branches...” (par. 0025).
Luick (US 2007/0186073 A1) teaches…" In one embodiment of the invention,
D-cache miss information (MIS and/or HIS bits) may be stored in a special cache, referred to as a shadow cache. For example, when a load instruction results in a D- cache miss, an entry may be placed in the shadow cache…” (par. 0106).
INFORMATION CONCERNING CLAIMS:
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
7. Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
8. Independent claim 1 recites, in part, limitation:
“a memory coupled to the second cache controller and configured to store a set of data that identifies the set of cache entries stored in the first cache memory” (emphasis added).
The claimed specification does not appear to describe/support the limitation as claimed. Claims 2-11 are rejected at least by virtue of their dependency from the base independent claim 1.
9. Independent claim 12 recites, in part, limitation:
“wherein the first cache controller is configured to: store a first set of cache entries in the first cache memory” (emphasis added). The claimed specification does not appear to describe/support the limitation as claimed. Claims 13-16 are rejected at least by virtue of their dependency from the base independent claim 12.
10. Independent claim 17 recites, in part, limitation:
“determining, by the first cache controller, whether the first request is a hit in a cache memory of a second cache level using a tag memory of the first cache level” The claimed specification does not appear to describe/support the limitation as claimed. Claims 18-20 are rejected at least by virtue of their dependency from the base independent claim 17.
Double Patenting
11. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
12. Claims 1-7 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 9, and 13 of U.S. Patent No. 12,197,331 B2 (hereinafter “the patent”). Although the claims at issue are not identical, they are not patentably distinct from each other because:
For example the claim 1 of current patent recites a set of data identifies a set of cache entries while claim 1 of the patent recite a set of addresses associated with a cache entries. The claims of the instant application recites L1 cache and L2 cache while claims of the patent recite first level cache and second level cache. Claim 3 of instant patent recites the first cache level is a level one data (L1D) cache level while claim of the patent recite first level cache, which may comprise first level data cache. The Examiner respectfully submits these minor differences do not make the claims patentably distinct from each other
13. Claims 1-7 of the instant application are compared with claims 1, 9, and 13 of the patent in the following table:
US Patent 12,197,331 B2
US Application 19/017,952
1. An integrated circuit device comprising:
a processor core;
a cache system coupled to the processor core that includes:
a first cache subsystem that includes:
a first cache controller coupled to the processor core;
a main cache memory coupled to the first cache controller and configured to store a first set of cache entries; and a victim cache memory coupled to the first cache controller and configured to store a second set of cache entries; and
a second cache subsystem that includes:
a second cache controller coupled to the first cache controller;
a shadow main cache memory coupled to the second cache controller and configured to store a first set of addresses associated with the first set of cache entries;
and a shadow victim cache memory coupled to the second cache controller and configured to store a second set of addresses associated with the second set of cache entries.
Claim 9:
wherein the second cache controller is configured to: receive a read request for a set of data; determine whether the read request is associated with a hit in either the first set of addresses or the second set of addresses; and
based on the read request being associated with a hit, provide a snoop request for the set of data to the first cache controller.
1. A circuit device comprising:
a processor core;
a first cache controller coupled to the processor core, wherein the first cache controller is associated with a first cache level;
a first cache memory coupled to the first cache controller, wherein: the first cache memory is associated with the first cache level; and the first cache memory is configured to store a set of cache entries;
a second cache controller coupled to the first cache controller, wherein the second cache controller is associated with a second cache level; and
a memory coupled to the second cache controller and configured to store a set of data that identifies the set of cache entries stored in the first cache memory;
wherein the second cache controller is configured to: receive a first request; determine, based on the set of data, whether the first request is a hit in the set of cache entries stored in the first cache memory; and
based on the first request being a hit in the set of cache entries, provide a second request associated with the first request to the first cache controller.
13. A method comprising: storing a set of cache entries in a cache memory of a first level cache; storing a set of identifiers associated with the set of cache entries in a shadow cache memory of a second level cache …
2. The circuit device of claim 1,
wherein: the first cache level is a level one (L1) cache level; and the second cache level is a level two (L2) cache level.
13. A method comprising: storing a set of cache entries in a cache memory of a first level cache; …
3.The circuit device of claim 2,
wherein the first cache level is a level one data (L1D) cache level.
9. The integrated circuit device of claim 1, wherein the second cache controller is configured to: receive a read request for a set of data;
determine whether the read request is associated with a hit in either the first set of addresses or the second set of addresses; and based on the read request being associated with a hit, provide a snoop request for the set of data to the first cache controller.
5. The circuit device of claim 1,
wherein: the first request is a read request; and
the second request is a snoop read request.
19. The method of claim 13 further comprising: receiving a first snoop request;
determining whether the first snoop request is associated with a hit in the set of identifiers; and based on the first snoop request being associated with a hit, providing a second snoop request for the set of data to the first level cache.
6. The circuit device of claim 5,
wherein the first request is a snoop read request.
11. The integrated circuit device of claim 1,
wherein the second cache controller is configured to: receive a write request for a first set of data;
determine whether the write request is associated with a hit in either the first set of addresses or the second set of addresses; and
based on the write request being associated with a hit,
provide a snoop and invalidate request to the first cache controller.
7. The circuit device of claim 1,
wherein: the first request is a write request; and
the second request is a snoop read and invalidate request.
Direction OF FUTURE CORRESPONDENCES:
14. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HASHEM FARROKH whose telephone number is (571)272-4193. The examiner can normally be reached Monday through Friday from 8:30 am - 5:00 pm.
15. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Mr. Tim Vo can be reached on (571)272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HASHEM FARROKH/Primary Examiner, Art Unit 2138
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