DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 22- 41 are pending.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 22- 41 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11914888. Although the claims at issue are not identical, they are not patentably distinct from each other because as illustrated in the table below. Both the present application and the associated patent teaches the management of data rate transitions between memory elements using a rate alignment module, where the output bandwidth is greater than the input bandwidth. The difference in the present application and the related patent is the present application is embodied in integrated circuit, while the patent’s embodiment is broader memory modules. It would be obvious to one of ordinary skill in the art that the present application is a cost-effective solution of rate alignment.
Present Application
US11914888
22. An integrated-circuit memory component comprising: a first memory die; and a second die disposed in a stack with the first memory die, the second die having: a first interface coupled to receive a first set of N data bits from the first memory die over a first memory-die readout interval, N being a nonzero integer; and a second interface to output the first set of N data bits from the integrated-circuit memory component over a first data-output interval briefer than the first memory- die readout interval.
1. A memory component comprising: a first core storage array to provide successive sets of N data bits over successive core-readout intervals, respectively, N being a nonzero integer; and output circuitry to receive the successive sets of N data bits from the first core storage array and to output the successive sets of N data bits from the memory component over successive data-output intervals, respectively, each one of the data-output intervals being briefer than any one of the core-readout intervals.
32. A method of operation within an integrated-circuit memory component having a first memory die stacked on a second die, the method comprising: receiving, via a first interface of the second die, a first set of N data bits from the first memory die over a first memory-die readout interval, N being a nonzero integer; and outputting the first set of N data bits from the integrated-circuit memory component via a second interface of the second die over a first data-output interval briefer than the first memory-die readout interval.
11. A method of operation within a memory component having a first core storage array and output circuitry, the method comprising: providing successive sets of N data bits from the first core storage to the output circuitry over successive core-readout intervals, respectively, N being a nonzero integer; and outputting the successive sets of N data bits from the memory component via the output circuitry over successive data-output intervals, respectively, each one of the data-output intervals being briefer than any one of the core-readout intervals.
43. An integrated-circuit memory component comprising: a first memory die; and a second die disposed in a stack with the first memory die, the second die having: means for receiving a first set of N data bits from the first memory die over a first memory-die readout interval, N being a nonzero integer; and means for outputting the first set of N data bits from the integrated-circuit memory component over a first data-output interval briefer than the first memory-die readout interval.
21. A memory component comprising: a first core storage array to provide successive sets of N data bits over successive core-readout intervals, respectively, N being a nonzero integer; and means for receiving the successive sets of N data bits from the first core storage array and for outputting the successive sets of N data bits from the memory component over successive data-output intervals, respectively, each one of the data-output intervals being briefer than any one of the core-readout intervals.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US20160041785, US20160082383, and 20140099106 among others teach rate alignment among memory modules
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER ANTHONY DALEY whose telephone number is (571)272-3625. The examiner can normally be reached 7 - 3:30 pm.
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/C.A.D/Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184