Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Foreign Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been placed in the file of record.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/forms/. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-26 of U.S. Patent No. 9728245.
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Current Application # 19018307
US Pat # 12229447
For example:
Claim 1:
1. A nonvolatile semiconductor memory, comprising: a first memory string; a first interconnect coupled to one end of the first memory string; a second interconnect coupled to another end of the first memory string; a first circuit configured to control the first interconnect in accordance with first data; and a second circuit coupled to the second interconnect, the second circuit including a current mirror circuit, and the second circuit being configured to output second data based on an amount of a current flowing through the second interconnect.
For example:
Claim 1:
A nonvolatile semiconductor memory comprising: a plurality of memory cells; a plurality of bit lines connected to the plurality of memory cells; a first circuit configured to control the plurality of bit lines according to first data; a source line commonly connected to first ends of the plurality of bit lines; and a second circuit connected to the source line and configured to detect second data according to a current amount in the source line, wherein: the second circuit includes a third circuit and a fourth circuit, the third circuit is configured to compare a first voltage with a second voltage, the first voltage being a reference voltage, and the second voltage being a voltage of the source line based on the current amount in the source line, and the fourth circuit is configured to digitally convert the current amount in the source line.
7. The nonvolatile semiconductor memory according to claim 6, wherein the fourth circuit further includes: a sixth transistor having a first end connected to the power supply voltage and a second end connected to a gate of the sixth transistor; a seventh transistor having a first end connected to the power supply voltage and configured as a current mirror with the sixth transistor;
Even though the claims at issue are not identical but overall scope of the claims are identical and they are not patentably distinct from each other. For example, the above limitation “the second circuit including a current mirror circuit” in current application 19018307 and the limitation “configured as a current mirror with the sixth transistor” in US Pat # 12229447 are not identical but they are not patentably distinct from each other. Because, current mirror is in the fourth circuits which includes second circuits.
Claims 1-20 would be allowable if the double patenting rejection set forth in this office action is overcome.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attachment.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824
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