DETAILED ACTION
Claims 2-21 are present for examination.
Claims 2, 5-4, 10, 14, 16 and 18 have been amended.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Terminal Disclaimer
The terminal disclaimer filed on 05/08/2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of U.S. Patent No. 10,592,120, U.S. Patent No. 11,809712 and U.S. Patent No. 12,197,7931 has been reviewed and is accepted. The terminal disclaimer has been recorded.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsui (US2004/0105292) in view of Perego et al. (US2011/0219197).
With respect claim 2, Matsui teaches a module substrate configured to mount to a motherboard (see Figs. 1 and 2 and paragraphs 136-137; memory module 103a mounted in motherboard 100. Memory module 103a is provided on a module board thereof with a buffer 105);
buffer circuitry mounted on the module substrate (see Figs. 1-2 and 4, and paragraphs 137; memory modules 103 are provided on a module board with buffers 105), the buffer circuitry comprising:
a first data buffer circuit comprising a primary interface (see paragraphs 137-138; data wiring 111 is connected from the memory controller 101 to the buffer 105 of the memory module 103a) to receive first write data from the memory controller (see paragraph 28; data is transmitted/received bidirectionally in the data wiring 111 between the controller and the buffer), the first data buffer circuit comprising a first secondary interface coupled to the first memory chip (see paragraph 140; the buffer 105 in each memory module 103 and the DRAMs 110 mounted in the subject memory module 103 are connected together via internal data wiring 111’);
a second data buffer circuit comprising a second secondary interface coupled to the second memory chip (see Figs. 1-2 and paragraph 140; the buffer 105 (i.e., buffer in module 103b) in each memory module 103 and the DRAMs 110 mounted in the subject memory module 103 are connected together via internal data wiring 111'), the second data buffer circuit coupled to the first data buffer circuit via a data distribution path (see paragraph 19; buffers on the adjacent memory modules are connected to each other via data lines in a point-to-point fashion) and to receive the first write data via the data distribution path (see paragraph 29; the buffer of each module is connected to the buffer of another module and/or the controller via data wiring for data transmission); and
wherein the second memory chip receives the first write data from the second data buffer circuit (see Figs. 1-2 and paragraphs 212-213 and 235; the buffer 105 (i.e., second buffer 105 in memory module 103b) is provided with a DQ output driver 301 for outputting data to the DRAM 110, and a data receiver 302 for receiving read data from the DRAM 110).
Even though Matsui teaches memory module 103a is provided on a module board thereof with a buffer 105 and a plurality of DRAMs 110 (i.e., first and second memory devices) (see Figs. 1 and 2, paragraph 137). Matsui does not explicitly teach a first integrated circuit (IC) memory chip and a second integrated circuit (IC) memory chip, the first IC memory chip and the second IC memory chip disposed on the module substrate.
However, Perego et al. teaches where the first memory is a memory module; and where the first memory includes a first group of one or more integrated circuit memory devices (see claims 12 and 28).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the module taught by Matsui to include the above mentioned to improve operation of the system (see Perego, page 2, paragraph 39, page 13, paragraph 144).
With respect claim 3, Matsui teaches wherein: the primary interface of the first data buffer circuit is to couple to one of a group of links associated with the memory controller (see paragraphs 137-138; data wiring 111 is connected from the memory controller 101 to the buffer 105 of the memory module 103a).
With respect claim 4, Matsui teaches wherein: the memory module couples to the memory controller solely via the primary interface of the first data buffer circuit in a point-to-point configuration (see paragraph 147; data wiring 111 is connected point-to-point between the memory controller 101 and the memory module 103).
With respect claim 5, Matsui teaches wherein: the primary interface of the first data buffer circuit is to receive second write data from the memory controller (see paragraph 28; data is transmitted/received bidirectionally in the data wiring 111 between the controller and the buffer).
Matsui does not teach wherein the first IC memory chip is to receive the second write data from the first secondary interface of the first data buffer circuit concurrent with the second IC memory chip receiving the first write data from the second secondary interface of the second data buffer circuit.
However, Perego et al. teaches wherein the CA1 or CA2 port may include two signal lines capable of carrying two bits of information in parallel…each memory device 1204 and 1206 may be independently accessed via the dedicated CA line (see pages 7-8, paragraph 93 and 94; and page 14, paragraph 162).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the module taught by Matsui to include the above mentioned to improve operation of the system (see Perego, page 2, paragraph 39, page 13, paragraph 144).
With respect claim 6, Matsui does not teach wherein: the first IC memory chip is to receive the second write data during a first memory access time interval; and wherein the second IC memory chip is to receive the first write data during a second memory access time interval that at least partially overlaps the first memory access time interval.
However, Perego et al. teaches wherein when the memory system 1200 is in the first operation mode, the controller logic 1222 generates the CA signals (CA1 and CA2) with a first signaling rate (e.g., 32 bits per one tRR interval, where tRR represents a minimum time interval between independent row accesses to a particular memory device). The CA1 or CA2 port may include multiple signal links capable of carrying multiple bits of information in parallel. In the example of FIG. 12, the CA1 or CA2 port may include two signal lines capable of carrying two bits of information in parallel, or the CA1 or CA2 port is two bits wide. So, when the CA signaling rate is 32 bits/ tRR, the CA1 or CA2 port may carry a maximum of 64 CA bits during one tRR interval or during 32 tBIT-CA intervals, wherein tBIT-CA represents a bit interval in a CA signal (see page 7, paragraph 93).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the module taught by Matsui to include the above mentioned to improve operation of the system (see Perego, page 2, paragraph 39, page 13, paragraph 144).
With respect claim 7, Matsui teaches wherein: the primary interface of the first data buffer circuit is to receive the first write data from the memory controller in accordance with a dynamic random access memory (DRAM) protocol (see paragraph 141; DRAM 110 is a DRAM of a x-8 configuration that can write and read data per 8 bits, data transmission/reception is performed on the unit of 8 bits).
With respect claim 8, Matsui teaches wherein: the primary interface of the first data buffer circuit is to operate at a first data rate (see paragraph 36 and 151; the data wiring 111 is fed with data and command/address signals at a transmission speed of 2.66 Gbps); and
the first secondary interface of the first data buffer circuit and the second secondary interface of the second data buffer circuit are to operate at a second data rate that is less than the first data rate (see paragraph 36 and 150-151; transmission speeds of the internal data wiring 111' is 1.33 Gbps).
With respect claim 9, Matsui teaches wherein: the second data rate comprises half the first data rate (see paragraphs 36 and 150-151; the data wiring 111 is fed with data and command/address signals at a transmission speed of 2.66 Gbps…transmission speeds of the internal data wiring 111' is 1.33 Gbps).
With respect claim 10, Matsui teaches a memory module, the memory module configured to mount to a motherboard (see Figs. 1 and 2 and paragraphs 136-137; memory module 103a mounted in motherboard 100. Memory module 103a is provided on a module board thereof with a buffer 105), the method comprising:
buffering a first memory chip and a second memory chip from a memory controller (see Figs. 1-2 and 4, and paragraphs 137; memory modules 103 are provided on a module board with buffers 105. Also in paragraph 148; buffer 105 provided on memory module 103a has a function of receiving a data signal or a command/address signal from the memory controller 101), the buffering comprising
interfacing with a memory controller via a group of links coupled to a primary interface of a first data buffer circuit (see paragraphs 137-138; data wiring 111 is connected from the memory controller 101 to the buffer 105 of the memory module 103a. Also in paragraph 28; data is transmitted/received bidirectionally in the data wiring 111 between the controller and the buffer);
interfacing with the first memory chip via a first secondary interface of the first data buffer circuit (see paragraph 140; the buffer 105 in each memory module 103 and the DRAMs 110 mounted in the subject memory module 103 are connected together via internal data wiring 111’) and the second memory chip via a second secondary interface of a second data buffer circuit (see Figs. 1-2 and paragraph 140; the buffer 105 (i.e., buffer in module 103b) in each memory module 103 and the DRAMs 110 mounted in the subject memory module 103 are connected together via internal data wiring 111');
distributing first write data received at the primary interface of the first data buffer circuit, from the memory controller, to the second data buffer circuit (see paragraph 29; the buffer of each module is connected to the buffer of another module and/or the controller via data wiring for data transmission); and
transferring the first write data from the second secondary interface of the second data buffer circuit to the second memory device (see Figs. 1-2 and paragraphs 212-213 and 235; the buffer 105 (i.e., second buffer 105 in memory module 103b) is provided with a DQ output driver 301 for outputting data to the DRAM 110, and a data receiver 302 for receiving read data from the DRAM 110).
Even though Matsui teaches memory module 103a is provided on a module board thereof with a buffer 105 and a plurality of DRAMs 110 (i.e., first and second memory devices) (see Figs. 1 and 2, paragraph 137). Matsui does not explicitly teach a first integrated circuit (IC) memory chip and a second integrated circuit (IC) memory chip, the first IC memory chip and the second IC memory chip disposed on the module substrate.
However, Perego et al. teaches where the first memory is a memory module; and where the first memory includes a first group of one or more integrated circuit memory devices (see claims 12 and 28).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Matsui to include the above mentioned to improve operation of the system (see Perego, page 2, paragraph 39, page 13, paragraph 144).
With respect claim 11, Matsui teaches wherein interfacing with the memory controller further comprises: coupling the primary interface of the first data buffer circuit to one of a group of links associated with the memory controller (see paragraphs 137-138; data wiring 111 is connected from the memory controller 101 to the buffer 105 of the memory module 103a).
With respect claim 12, Matsui teaches wherein interfacing with the memory controller comprises: coupling the memory module to the memory controller solely via the primary interface of the first data buffer circuit in a point-to-point configuration (see paragraph 147; data wiring 111 is connected point-to-point between the memory controller 101 and the memory module 103).
With respect claim 13, Matsui teaches receiving, with the primary interface of the first data buffer circuit, second write data from the memory controller (see paragraph 28; data is transmitted/received bidirectionally in the data wiring 111 between the controller and the buffer).
Matsui does not teach receiving, with the first memory device, the second write data from the first secondary interface of the first data buffer circuit concurrent with the second memory device receiving the first write data from the second secondary interface of the second data buffer circuit.
However, Perego et al. teaches wherein the CA1 or CA2 port may include two signal lines capable of carrying two bits of information in parallel…each memory device 1204 and 1206 may be independently accessed via the dedicated CA line (see pages 7-8, paragraph 93 and 94; and page 14, paragraph 162).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Matsui to include the above mentioned to improve operation of the system (see Perego, page 2, paragraph 39, page 13, paragraph 144).
With respect claim 14, Matsui does not teach receiving, with the first IC memory chip, the second write data during a first memory access time interval; and receiving, with the second IC memory chip, the first write data during a second memory access time interval that at least partially overlaps the first memory access time interval.
However, Perego et al. teaches wherein when the memory system 1200 is in the first operation mode, the controller logic 1222 generates the CA signals (CA1 and CA2) with a first signaling rate (e.g., 32 bits per one tRR interval, where tRR represents a minimum time interval between independent row accesses to a particular memory device). The CA1 or CA2 port may include multiple signal links capable of carrying multiple bits of information in parallel. In the example of FIG. 12, the CA1 or CA2 port may include two signal lines capable of carrying two bits of information in parallel, or the CA1 or CA2 port is two bits wide. So, when the CA signaling rate is 32 bits/ tRR, the CA1 or CA2 port may carry a maximum of 64 CA bits during one tRR interval or during 32 tBIT-CA intervals, wherein tBIT-CA represents a bit interval in a CA signal (see page 7, paragraph 93).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Matsui to include the above mentioned to improve operation of the system (see Perego, page 2, paragraph 39, page 13, paragraph 144).
With respect claim 15, Matsui teaches wherein: receiving, with the primary interface of the first data buffer circuit, the first write data and the second write data from the memory controller comprises receiving the first write data and the second write data in accordance with a dynamic random access memory (DRAM) protocol (see paragraph 141; DRAM 110 is a DRAM of a x-8 configuration that can write and read data per 8 bits, data transmission/reception is performed on the unit of 8 bits).
With respect claim 16, Matsui teaches a memory module, the memory module configured to mount to a motherboard (see Figs. 1 and 2 and paragraphs 136-137; memory module 103a mounted in motherboard 100. Memory module 103a is provided on a module board thereof with a buffer 105), the IC buffer chipset comprising:
a first IC data buffer chip (see paragraph 176; buffer chips) comprising a primary interface (see paragraphs 137-138; data wiring 111 is connected from the memory controller 101 to the buffer 105 of the memory module 103a) to receive first write data from a memory controller (see paragraph 28; data is transmitted/received bidirectionally in the data wiring 111 between the controller and the buffer), the first IC data buffer chip comprising a first secondary interface coupled to a first memory chip mounted on the memory module substrate (see paragraph 140; the buffer 105 in each memory module 103 and the DRAMs 110 mounted in the subject memory module 103 are connected together via internal data wiring 111’);
a second IC data buffer chip (see paragraph 176; buffer chips) comprising a second secondary interface coupled to a second memory chip mounted on the memory module substrate (see Figs. 1-2 and paragraph 140; the buffer 105 (i.e., buffer in module 103b) in each memory module 103 and the DRAMs 110 mounted in the subject memory module 103 are connected together via internal data wiring 111'), the second IC data buffer chip coupled to the first IC data buffer chip via a data distribution path (see paragraph 19; buffers on the adjacent memory modules are connected to each other via data lines in a point-to-point fashion) and to receive the first write data via the data distribution path (see paragraph 29; the buffer of each module is connected to the buffer of another module and/or the controller via data wiring for data transmission); and
wherein the second secondary interface of the second IC data buffer chip is to transfer the first write data to the second memory device (see Figs. 1-2 and paragraphs 212-213 and 235; the buffer 105 (i.e., second buffer 105 in memory module 103b) is provided with a DQ output driver 301 for outputting data to the DRAM 110, and a data receiver 302 for receiving read data from the DRAM 110).
Even though Matsui teaches memory module 103a is provided on a module board thereof with a buffer 105 and a plurality of DRAMs 110 (i.e., first and second memory devices) (see Figs. 1 and 2, paragraph 137). Matsui does not explicitly teach a first integrated circuit (IC) memory chip and a second integrated circuit (IC) memory chip, the first IC memory chip and the second IC memory chip disposed on the module substrate.
However, Perego et al. teaches where the first memory is a memory module; and where the first memory includes a first group of one or more integrated circuit memory devices (see claims 12 and 28).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the circuit taught by Matsui to include the above mentioned to improve operation of the system (see Perego, page 2, paragraph 39, page 13, paragraph 144).
With respect claim 17, Matsui teaches wherein: solely the primary interface of the first IC data buffer chip is to couple to the memory controller in a point-to-point configuration (see paragraph 147; data wiring 111 is connected point-to-point between the memory controller 101 and the memory module 103); and
the second IC data buffer chip is to indirectly couple to the memory controller via the first IC data buffer chip (see paragraph 29; the buffer of each module is connected to the buffer of another module and/or the controller via data wiring for data transmission).
With respect claim 18, Matsui teaches wherein: the primary interface of the first IC data buffer chip is to receive second write data from the memory controller (see paragraph 28; data is transmitted/received bidirectionally in the data wiring 111 between the controller and the buffer).
Matsui does not teach wherein the first IC data buffer chip is to transfer the second write data to the first IC memory chip concurrent with the second IC data buffer chip transferring the first write data to the second IC memory chip.
However, Perego et al. teaches wherein the CA1 or CA2 port may include two signal lines capable of carrying two bits of information in parallel…each memory device 1204 and 1206 may be independently accessed via the dedicated CA line (see pages 7-8, paragraph 93 and 94; and page 14, paragraph 162).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the circuit taught by Matsui to include the above mentioned to improve operation of the system (see Perego, page 2, paragraph 39, page 13, paragraph 144).
With respect claim 19, Matsui teaches wherein: the primary interface of the first IC data buffer chip is to receive the first write data from the memory controller in accordance with a dynamic random access memory (DRAM) protocol (see paragraph 141; DRAM 110 is a DRAM of a x-8 configuration that can write and read data per 8 bits, data transmission/reception is performed on the unit of 8 bits).
With respect claim 20, Matsui teaches wherein: the primary interface of the first IC data buffer chip is to operate at a first data rate (see paragraph 36 and 151; the data wiring 111 is fed with data and command/address signals at a transmission speed of 2.66 Gbps); and
the first secondary interface of the first IC data buffer chip and the second secondary interface of the second IC data buffer chip are to operate at a second data rate that is less than the first data rate (see paragraph 36 and 150-151; transmission speeds of the internal data wiring 111' is 1.33 Gbps).
With respect claim 21, Matsui teaches wherein: the second data rate comprises half the first data rate (see paragraphs 36 and 150-151; the data wiring 111 is fed with data and command/address signals at a transmission speed of 2.66 Gbps…transmission speeds of the internal data wiring 111' is 1.33 Gbps).
Response to Arguments
Applicant’s representative argues, in pages 9-10, that Matsui distinguishes over claim 2 because Matsui teaches multiple memory module substrates, and not a singular "module substrate" as recited in the claim.
In response: The examiner disagrees. Even though the Matsui references teach each single separate module that is mounted in the motherboard (see Figs. 1 and 2 and paragraphs 136-137; memory module 103a mounted in motherboard 100. Memory module 103a is provided on a module board thereof with a buffer 105).
Applicant's arguments with respect to claims 2-21 have been considered but are moot in view of the new ground(s) of rejection, necessitated by amendment.
Applicant’s arguments, see page 8, filed 05/08/2026, with respect to the objection of the Specification have been fully considered and are persuasive. The objection of the specification has been withdrawn.
Applicant’s arguments, see pages 11-12, filed 05/08/2026, with respect to the Double Patenting rejections of claims 2-21 have been fully considered and are persuasive. The rejections of the claims have been withdrawn.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Halbert et al. (US 6,742,098) teaches dual-port buffer-to-memory interface.
Ware et al. (US2011/0016278) teaches independent threading of memory devices disposed on memory modules.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARACELIS RUIZ whose telephone number is (571)270-1038. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald G. Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ARACELIS RUIZ/Primary Examiner, Art Unit 2139
Prosecution Insights