DETAILED ACTION
Claims 2-21 are present for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/13/2025 is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities:
In paragraph 1, lines 1-2, where it says “No. 18/492,296, filed October 23,2023, which is a…” should be --No. 18/492,296, filed October 23,2023, now U.S. Patent No. 12,197,731, which is a…--.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2-4, 7-12 and 15 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, 6, 9-10 and 14 of U.S. Patent No. 12,197,731 in view of Matsui (US2004/0105292).
Claim 2 of the present application corresponds to claim 1 of the ‘731 patent, where “A memory module…” corresponds to claim 1, line 1 of the ‘731 patent; “a module substrate…” corresponds to claim 1, line 2 of the ‘731 patent; “a first memory device and a second memory device…” corresponds to claim 1, lines 3-5 of the ‘731 patent; “a buffer circuitry …” corresponds to claim 1, lines 6-7 of the ‘731 patent; and “a first data buffer circuit comprising a primary interface …” corresponds to claim 1, lines 8-12 of the ‘731 patent.
The ‘731 patent does not teach a second data buffer circuit comprising a second secondary interface coupled to the second memory device, the second data buffer circuit coupled to the first data buffer circuit via a data distribution path and to receive the first write data via the data distribution path; and wherein the second memory device receives the first write data from the second data buffer circuit.
However, Matsui teaches a second data buffer circuit comprising a second secondary interface coupled to the second memory device (see Figs. 1-2 and paragraph 140; the buffer 105 (i.e., buffer in module 103b) in each memory module 103 and the DRAMs 110 mounted in the subject memory module 103 are connected together via internal data wiring 111'), the second data buffer circuit coupled to the first data buffer circuit via a data distribution path (see paragraph 19; buffers on the adjacent memory modules are connected to each other via data lines in a point-to-point fashion) and to receive the first write data via the data distribution path (see paragraph 29; the buffer of each module is connected to the buffer of another module and/or the controller via data wiring for data transmission); and wherein the second memory device receives the first write data from the second data buffer circuit (see Figs. 1-2 and paragraphs 212-213 and 235; the buffer 105 (i.e., second buffer 105 in memory module 103b) is provided with a DQ output driver 301 for outputting data to the DRAM 110, and a data receiver 302 for receiving read data from the DRAM 110).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the module taught by ‘731 patent to include the above mentioned to provide a data transfer method that can transfer data at high speed (see Matsui, paragraph 16).
Claim 3 of the present application corresponds to claim 1 of the ‘731 patent, where “the primary interface of the first data buffer circuit…” corresponds to claim 1, lines 8-9 of the ‘731 patent.
Claim 4 of the present application corresponds to claim 2 of the ‘731 patent, where “wherein: the memory module couples to the memory controller solely via the primary interface…” corresponds to claim 2, lines 1-4 of the ‘731 patent.
Claim 7 of the present application corresponds to claim 6 of the ‘731 patent, where “wherein: the primary interface of the first data buffer circuit is to receive the first write data…” corresponds to claim 6, lines 1-5 of the ‘731 patent.
Claim 8: The ‘731 patent does not teach wherein: the primary interface of the first data buffer circuit is to operate at a first data rate; and the first secondary interface of the first data buffer circuit and the second secondary interface of the second data buffer circuit are to operate at a second data rate that is less than the first data rate.
However, Matsui teaches wherein: the primary interface of the first data buffer circuit is to operate at a first data rate (see paragraph 36 and 151; the data wiring 111 is fed with data and command/address signals at a transmission speed of 2.66 Gbps); and the first secondary interface of the first data buffer circuit and the second secondary interface of the second data buffer circuit are to operate at a second data rate that is less than the first data rate (see paragraph 36 and 150-151; transmission speeds of the internal data wiring 111' is 1.33 Gbps).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the module taught by ‘731 patent to include the above mentioned to provide a data transfer method that can transfer data at high speed (see Matsui, paragraph 16).
Claim 9: The ’731 patent does not teach wherein: the second data rate comprises half the first data rate.
However, Matsui teaches wherein: the second data rate comprises half the first data rate (see paragraphs 36 and 150-151; the data wiring 111 is fed with data and command/address signals at a transmission speed of 2.66 Gbps…transmission speeds of the internal data wiring 111' is 1.33 Gbps).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the module taught by ‘731 patent to include the above mentioned to provide a data transfer method that can transfer data at high speed (see Matsui, paragraph 16).
Claim 10 of the present application corresponds to claim 9 of the ‘731 patent, where “A method…” corresponds to claim 9, lines 1-2 of the ‘731 patent; “buffering a first memory device and a second memory…” corresponds to claim 9, lines 3-5 of the ‘731 patent; “interfacing with a memory controller via a group of links…” corresponds to claim 9, lines 6-7 of the ‘731 patent; and “interfacing with the first memory device via a first secondary interface…” corresponds to claim 9, lines 8-10 of the ‘731 patent.
The ’731 patent does not teach interfacing with the second memory device via a second secondary interface of a second data buffer circuit; distributing first write data received at the primary interface of the first data buffer circuit, from the memory controller, to the second data buffer circuit; and transferring the first write data from the second secondary interface of the second data buffer circuit to the second memory device.
However, Matsui teaches interfacing with the second memory device via a second secondary interface of a second data buffer circuit (see Figs. 1-2 and paragraph 140; the buffer 105 (i.e., buffer in module 103b) in each memory module 103 and the DRAMs 110 mounted in the subject memory module 103 are connected together via internal data wiring 111'); distributing first write data received at the primary interface of the first data buffer circuit, from the memory controller, to the second data buffer circuit (see paragraph 29; the buffer of each module is connected to the buffer of another module and/or the controller via data wiring for data transmission); and transferring the first write data from the second secondary interface of the second data buffer circuit to the second memory device (see Figs. 1-2 and paragraphs 212-213 and 235; the buffer 105 (i.e., second buffer 105 in memory module 103b) is provided with a DQ output driver 301 for outputting data to the DRAM 110, and a data receiver 302 for receiving read data from the DRAM 110).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by ‘731 patent to include the above mentioned to provide a data transfer method that can transfer data at high speed (see Matsui, paragraph 16).
Claim 11 of the present application corresponds to claim 9 of the ‘731 patent, where “wherein interfacing with the memory controller…” corresponds to claim 9, lines 6-7 of the ‘731 patent.
Claim 12 of the present application corresponds to claim 10 of the ‘731 patent, where “wherein interfacing with the memory controller comprises: coupling the memory module…” corresponds to claim 10, lines 1-5 of the ‘731 patent.
Claim 15 of the present application corresponds to claim 14 of the ‘731 patent, where “herein: receiving, with the primary interface of the first data buffer circuit…” corresponds to claim 14, lines 1-5 of the ‘731 patent.
Claims 5-6 and 13-14 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, 6, 9-10 and 14 of U.S. Patent No. 12,197,731 in view of Matsui (US2004/0105292) and further in view of Perego et al. (US2011/0219197).
Claim 5: The ‘731 patent does not teach wherein: the primary interface of the first data buffer circuit is to receive second write data from the memory controller; and wherein the first memory device is to receive the second write data from the first secondary interface of the first data buffer circuit concurrent with the second memory device receiving the first write data from the second secondary interface of the second data buffer circuit.
However, Matsui teaches wherein: the primary interface of the first data buffer circuit is to receive second write data from the memory controller (see paragraph 28; data is transmitted/received bidirectionally in the data wiring 111 between the controller and the buffer).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the module taught by ‘731 patent to include the above mentioned to provide a data transfer method that can transfer data at high speed (see Matsui, paragraph 16).
The ’731 patent and Matsui do not teach wherein the first memory device is to receive the second write data from the first secondary interface of the first data buffer circuit concurrent with the second memory device receiving the first write data from the second secondary interface of the second data buffer circuit.
However, Perego et al. teaches wherein the CA1 or CA2 port may include two signal lines capable of carrying two bits of information in parallel…each memory device 1204 and 1206 may be independently accessed via the dedicated CA line (see pages 7-8, paragraph 93 and 94; and page 14, paragraph 162).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the module taught by ‘731 patent and Matsui to include the above mentioned to improve operation of the system (see Perego, page 2, paragraph 39, page 13, paragraph 144).
Claim 6: The ’731 patent and Matsui do not teach wherein: the first memory device is to receive the second write data during a first memory access time interval; and wherein the second memory device is to receive the first write data during a second memory access time interval that at least partially overlaps the first memory access time interval.
However, Perego et al. teaches wherein when the memory system 1200 is in the first operation mode, the controller logic 1222 generates the CA signals (CA1 and CA2) with a first signaling rate (e.g., 32 bits per one tRR interval, where tRR represents a minimum time interval between independent row accesses to a particular memory device). The CA1 or CA2 port may include multiple signal links capable of carrying multiple bits of information in parallel. In the example of FIG. 12, the CA1 or CA2 port may include two signal lines capable of carrying two bits of information in parallel, or the CA1 or CA2 port is two bits wide. So, when the CA signaling rate is 32 bits/ tRR, the CA1 or CA2 port may carry a maximum of 64 CA bits during one tRR interval or during 32 tBIT-CA intervals, wherein tBIT-CA represents a bit interval in a CA signal (see page 7, paragraph 93).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the module taught by ‘731 patent Matsui to include the above mentioned to improve operation of the system (see Perego, page 2, paragraph 39, page 13, paragraph 144).
Claim 13: The ‘731 patent does not teach with the primary interface of the first data buffer circuit, second write data from the memory controller; and receiving, with the first memory device, the second write data from the first secondary interface of the first data buffer circuit concurrent with the second memory device receiving the first write data from the second secondary interface of the second data buffer circuit.
However, Matsui teaches receiving, with the primary interface of the first data buffer circuit, second write data from the memory controller (see paragraph 28; data is transmitted/received bidirectionally in the data wiring 111 between the controller and the buffer).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by ‘731 patent to include the above mentioned to provide a data transfer method that can transfer data at high speed (see Matsui, paragraph 16).
The ‘731 patent and Matsui do not teach receiving, with the first memory device, the second write data from the first secondary interface of the first data buffer circuit concurrent with the second memory device receiving the first write data from the second secondary interface of the second data buffer circuit.
However, Perego et al. teaches wherein the CA1 or CA2 port may include two signal lines capable of carrying two bits of information in parallel…each memory device 1204 and 1206 may be independently accessed via the dedicated CA line (see pages 7-8, paragraph 93 and 94; and page 14, paragraph 162).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by ‘731 patent and Matsui to include the above mentioned to improve operation of the system (see Perego, page 2, paragraph 39, page 13, paragraph 144).
Claim 14: The ‘731 patent and Matsui do not teach receiving, with the first memory device, the second write data during a first memory access time interval; an receiving, with the second memory device, the first write data during a second memory access time interval that at least partially overlaps the first memory access time interval.
However, Perego et al. teaches wherein when the memory system 1200 is in the first operation mode, the controller logic 1222 generates the CA signals (CA1 and CA2) with a first signaling rate (e.g., 32 bits per one tRR interval, where tRR represents a minimum time interval between independent row accesses to a particular memory device). The CA1 or CA2 port may include multiple signal links capable of carrying multiple bits of information in parallel. In the example of FIG. 12, the CA1 or CA2 port may include two signal lines capable of carrying two bits of information in parallel, or the CA1 or CA2 port is two bits wide. So, when the CA signaling rate is 32 bits/ tRR, the CA1 or CA2 port may carry a maximum of 64 CA bits during one tRR interval or during 32 tBIT-CA intervals, wherein tBIT-CA represents a bit interval in a CA signal (see page 7, paragraph 93).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by ‘731 patent and Matsui to include the above mentioned to improve operation of the system (see Perego, page 2, paragraph 39, page 13, paragraph 144).
Claims 2-4 and 7-9 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2 and 4 of U.S. Patent No. 10,592,120 in view of Matsui (US2004/0105292).
Claim 2 of the present application corresponds to claims 1-2 of the ‘120 patent, where “A memory module…” corresponds to claim 1, line 1 of the ‘120 patent; “a module substrate…” corresponds to claim 1, line 2 of the ‘120 patent; “a first memory device and a second memory device…” corresponds to claim 1, lines 3-4 of the ‘120; “a buffer circuitry …” corresponds to claim 1, line 5 of the ‘120 patent; and “a first data buffer circuit comprising a primary interface…” corresponds to claim 1, lines 5-10 and claim 2, lines 1-4 of the ‘731 patent.
The ‘731 patent does not teach a second data buffer circuit comprising a second secondary interface coupled to the second memory device, the second data buffer circuit coupled to the first data buffer circuit via a data distribution path and to receive the first write data via the data distribution path; and wherein the second memory device receives the first write data from the second data buffer circuit.
However, Matsui teaches a second data buffer circuit comprising a second secondary interface coupled to the second memory device (see Figs. 1-2 and paragraph 140; the buffer 105 (i.e., buffer in module 103b) in each memory module 103 and the DRAMs 110 mounted in the subject memory module 103 are connected together via internal data wiring 111'), the second data buffer circuit coupled to the first data buffer circuit via a data distribution path (see paragraph 19; buffers on the adjacent memory modules are connected to each other via data lines in a point-to-point fashion) and to receive the first write data via the data distribution path (see paragraph 29; the buffer of each module is connected to the buffer of another module and/or the controller via data wiring for data transmission); and wherein the second memory device receives the first write data from the second data buffer circuit (see Figs. 1-2 and paragraphs 212-213 and 235; the buffer 105 (i.e., second buffer 105 in memory module 103b) is provided with a DQ output driver 301 for outputting data to the DRAM 110, and a data receiver 302 for receiving read data from the DRAM 110).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the module taught by ‘120 patent to include the above mentioned to provide a data transfer method that can transfer data at high speed (see Matsui, paragraph 16).
Claim 3 of the present application corresponds to claim 1 of the ‘120 patent, where “the primary interface of the first data buffer circuit…” corresponds to claim 1, lines 8-10 of the ‘120 patent.
Claim 4 of the present application corresponds to claim 4 of the ‘120 patent, where “wherein: the memory module couples to the memory controller solely via the primary interface…” corresponds to claim 4, lines 1-5 of the ‘120 patent.
Claim 7: The ‘120 patent does not teach wherein: the primary interface of the first data buffer circuit is to receive the first write data from the memory controller in accordance with a dynamic random access memory (DRAM) protocol.
However, Matsui teaches wherein: the primary interface of the first data buffer circuit is to receive the first write data from the memory controller in accordance with a dynamic random access memory (DRAM) protocol (see paragraph 141; DRAM 110 is a DRAM of a x-8 configuration that can write and read data per 8 bits, data transmission/reception is performed on the unit of 8 bits).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the module taught by ‘120 patent to include the above mentioned to provide a data transfer method that can transfer data at high speed (see Matsui, paragraph 16).
Claim 8: The ‘120 patent does not teach wherein: the primary interface of the first data buffer circuit is to operate at a first data rate; and the first secondary interface of the first data buffer circuit and the second secondary interface of the second data buffer circuit are to operate at a second data rate that is less than the first data rate.
However, Matsui teaches wherein: the primary interface of the first data buffer circuit is to operate at a first data rate (see paragraph 36 and 151; the data wiring 111 is fed with data and command/address signals at a transmission speed of 2.66 Gbps); and the first secondary interface of the first data buffer circuit and the second secondary interface of the second data buffer circuit are to operate at a second data rate that is less than the first data rate (see paragraph 36 and 150-151; transmission speeds of the internal data wiring 111' is 1.33 Gbps).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the module taught by ‘120 patent to include the above mentioned to provide a data transfer method that can transfer data at high speed (see Matsui, paragraph 16).
Claim 9: The ’120 patent does not teach wherein: the second data rate comprises half the first data rate.
However, Matsui teaches wherein: the second data rate comprises half the first data rate (see paragraphs 36 and 150-151; the data wiring 111 is fed with data and command/address signals at a transmission speed of 2.66 Gbps…transmission speeds of the internal data wiring 111' is 1.33 Gbps).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the module taught by ‘731 patent to include the above mentioned to provide a data transfer method that can transfer data at high speed (see Matsui, paragraph 16).
Claims 5-6 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, and 4 of U.S. Patent No. 10,592,120 in view of Matsui (US2004/0105292) and further in view of Perego et al. (US2011/0219197).
Claim 5: The ‘120 patent does not teach wherein: the primary interface of the first data buffer circuit is to receive second write data from the memory controller; and wherein the first memory device is to receive the second write data from the first secondary interface of the first data buffer circuit concurrent with the second memory device receiving the first write data from the second secondary interface of the second data buffer circuit.
However, Matsui teaches wherein: the primary interface of the first data buffer circuit is to receive second write data from the memory controller (see paragraph 28; data is transmitted/received bidirectionally in the data wiring 111 between the controller and the buffer).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the module taught by ‘120 patent to include the above mentioned to provide a data transfer method that can transfer data at high speed (see Matsui, paragraph 16).
The ’120 patent and Matsui do not teach wherein the first memory device is to receive the second write data from the first secondary interface of the first data buffer circuit concurrent with the second memory device receiving the first write data from the second secondary interface of the second data buffer circuit.
However, Perego et al. teaches wherein the CA1 or CA2 port may include two signal lines capable of carrying two bits of information in parallel…each memory device 1204 and 1206 may be independently accessed via the dedicated CA line (see pages 7-8, paragraph 93 and 94; and page 14, paragraph 162).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the module taught by ‘120 patent and Matsui to include the above mentioned to improve operation of the system (see Perego, page 2, paragraph 39, page 13, paragraph 144).
Claim 6: The ’120 patent and Matsui do not teach wherein: the first memory device is to receive the second write data during a first memory access time interval; and wherein the second memory device is to receive the first write data during a second memory access time interval that at least partially overlaps the first memory access time interval.
However, Perego et al. teaches wherein when the memory system 1200 is in the first operation mode, the controller logic 1222 generates the CA signals (CA1 and CA2) with a first signaling rate (e.g., 32 bits per one tRR interval, where tRR represents a minimum time interval between independent row accesses to a particular memory device). The CA1 or CA2 port may include multiple signal links capable of carrying multiple bits of information in parallel. In the example of FIG. 12, the CA1 or CA2 port may include two signal lines capable of carrying two bits of information in parallel, or the CA1 or CA2 port is two bits wide. So, when the CA signaling rate is 32 bits/ tRR, the CA1 or CA2 port may carry a maximum of 64 CA bits during one tRR interval or during 32 tBIT-CA intervals, wherein tBIT-CA represents a bit interval in a CA signal (see page 7, paragraph 93).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the module taught by ‘120 patent Matsui to include the above mentioned to improve operation of the system (see Perego, page 2, paragraph 39, page 13, paragraph 144).
Claims 16-17 and 19-21 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 15 and 17 of U.S. Patent No. 11,809,712 in view of Matsui (US2004/0105292).
Claim 16 of the present application corresponds to claim 15 of the ‘712 patent, where “An integrated circuit (IC) buffer…” corresponds to claim 15, line 1 of the ‘712 patent; “a first IC data buffer chip comprising…” corresponds to claim 15, lines 1-6 of the ‘712 patent.
The ‘712 patent does not teach a second IC data buffer chip comprising a second secondary interface coupled to a second memory device disposed on the memory module, the second IC data buffer chip coupled to the first IC data buffer chip via a data distribution path and to receive the first write data via the data distribution path; and wherein the second secondary interface of the second IC data buffer chip is to transfer the first write data to the second memory device.
However, Matsui teaches a second IC data buffer chip (see paragraph 176; buffer chips) comprising a second secondary interface coupled to a second memory device disposed on the memory module (see Figs. 1-2 and paragraph 140; the buffer 105 (i.e., buffer in module 103b) in each memory module 103 and the DRAMs 110 mounted in the subject memory module 103 are connected together via internal data wiring 111'), the second IC data buffer chip coupled to the first IC data buffer chip via a data distribution path (see paragraph 19; buffers on the adjacent memory modules are connected to each other via data lines in a point-to-point fashion) and to receive the first write data via the data distribution path (see paragraph 29; the buffer of each module is connected to the buffer of another module and/or the controller via data wiring for data transmission); and wherein the second secondary interface of the second IC data buffer chip is to transfer the first write data to the second memory device (see Figs. 1-2 and paragraphs 212-213 and 235; the buffer 105 (i.e., second buffer 105 in memory module 103b) is provided with a DQ output driver 301 for outputting data to the DRAM 110, and a data receiver 302 for receiving read data from the DRAM 110).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the circuit taught by ‘712 patent to include the above mentioned to provide a data transfer method that can transfer data at high speed (see Matsui, paragraph 16).
Claim 17 of the present application corresponds to claim 17 of the ‘712 patent, where “wherein: solely the primary interface of the first IC data buffer chip…” corresponds to claim 17, lines 1-4 of the ‘712 patent
The ‘712 patent does not teach the second IC data buffer chip is to indirectly couple to the memory controller via the first IC data buffer chip.
However, Matsui teaches wherein the second IC data buffer chip is to indirectly couple to the memory controller via the first IC data buffer chip (see paragraph 29; the buffer of each module is connected to the buffer of another module and/or the controller via data wiring for data transmission).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the circuit taught by ‘712 patent to include the above mentioned to provide a data transfer method that can transfer data at high speed (see Matsui, paragraph 16).
Claim 19: The ‘712 patent does not teach wherein: the primary interface of the first IC data buffer chip is to receive the first write data from the memory controller in accordance with a dynamic random access memory (DRAM) protocol.
However, Matsui teaches wherein: the primary interface of the first IC data buffer chip is to receive the first write data from the memory controller in accordance with a dynamic random access memory (DRAM) protocol (see paragraph 141; DRAM 110 is a DRAM of a x-8 configuration that can write and read data per 8 bits, data transmission/reception is performed on the unit of 8 bits).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the circuit taught by ‘712 patent to include the above mentioned to provide a data transfer method that can transfer data at high speed (see Matsui, paragraph 16).
Claim 20: The ‘712 patent does not teach wherein: the primary interface of the first IC data buffer chip is to operate at a first data rate; and the first secondary interface of the first IC data buffer chip and the second secondary interface of the second IC data buffer chip are to operate at a second data rate that is less than the first data rate.
However, Matsui teaches wherein: the primary interface of the first IC data buffer chip is to operate at a first data rate (see paragraph 36 and 151; the data wiring 111 is fed with data and command/address signals at a transmission speed of 2.66 Gbps); and the first secondary interface of the first IC data buffer chip and the second secondary interface of the second IC data buffer chip are to operate at a second data rate that is less than the first data rate (see paragraph 36 and 150-151; transmission speeds of the internal data wiring 111' is 1.33 Gbps).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the circuit taught by ‘712 patent to include the above mentioned to provide a data transfer method that can transfer data at high speed (see Matsui, paragraph 16).
Claim 21: The ‘712 patent does not teach wherein: the second data rate comprises half the first data rate.
However, Matsui teaches wherein: the second data rate comprises half the first data rate (see paragraphs 36 and 150-151; the data wiring 111 is fed with data and command/address signals at a transmission speed of 2.66 Gbps…transmission speeds of the internal data wiring 111' is 1.33 Gbps).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the circuit taught by ‘712 patent to include the above mentioned to provide a data transfer method that can transfer data at high speed (see Matsui, paragraph 16).
Claim 18 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 15 and 17 of U.S. Patent No. 11,809,712 in view of Matsui (US2004/0105292) and in further view Perego et al. (US2011/0219197).
Claim 18: The ‘712 patent does not teach wherein: the primary interface of the first IC data buffer chip is to receive second write data from the memory controller; and wherein the first IC data buffer chip is to transfer the second write data to the first memory device concurrent with the second IC data buffer chip transferring the first write data to the second memory device.
However, Matsui teaches wherein: the primary interface of the first IC data buffer chip is to receive second write data from the memory controller (see paragraph 28; data is transmitted/received bidirectionally in the data wiring 111 between the controller and the buffer).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the circuit taught by ‘712 patent to include the above mentioned to provide a data transfer method that can transfer data at high speed (see Matsui, paragraph 16).
The ‘712 patent and Matsui do not teach wherein the first IC data buffer chip is to transfer the second write data to the first memory device concurrent with the second IC data buffer chip transferring the first write data to the second memory device.
However, Perego et al. teaches wherein the CA1 or CA2 port may include two signal lines capable of carrying two bits of information in parallel…each memory device 1204 and 1206 may be independently accessed via the dedicated CA line (see pages 7-8, paragraph 93 and 94; and page 14, paragraph 162).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the circuit taught by ‘712 patent and Matsui to include the above mentioned to improve operation of the system (see Perego, page 2, paragraph 39, page 13, paragraph 144).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 2-4, 7-12, 15-17 and 19-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matsui (US2004/0105292).
With respect claim 2, Matsui teaches a module substrate (see Figs. 1 and 2 and paragraphs 137; memory module 103 is provided on a module board);
a first memory device and a second memory device (see Figs. 1-2 and 4, and paragraph 136; memory modules 103a and 103b), the first memory device and the second memory device disposed on the module substrate (see Figs. 1 and 2 and paragraphs 137; memory modules 103 are provided on a module board);
buffer circuitry disposed on the module substrate (see Figs. 1-2 and 4, and paragraphs 137; memory modules 103 are provided on a module board with buffers 105), the buffer circuitry comprising:
a first data buffer circuit comprising a primary interface (see paragraphs 137-138; data wiring 111 is connected from the memory controller 101 to the buffer 105 of the memory module 103a) to receive first write data from the memory controller (see paragraph 28; data is transmitted/received bidirectionally in the data wiring 111 between the controller and the buffer), the first data buffer circuit comprising a first secondary interface coupled to the first memory device (see paragraph 140; the buffer 105 in each memory module 103 and the DRAMs 110 mounted in the subject memory module 103 are connected together via internal data wiring 111’);
a second data buffer circuit comprising a second secondary interface coupled to the second memory device (see Figs. 1-2 and paragraph 140; the buffer 105 (i.e., buffer in module 103b) in each memory module 103 and the DRAMs 110 mounted in the subject memory module 103 are connected together via internal data wiring 111'), the second data buffer circuit coupled to the first data buffer circuit via a data distribution path (see paragraph 19; buffers on the adjacent memory modules are connected to each other via data lines in a point-to-point fashion) and to receive the first write data via the data distribution path (see paragraph 29; the buffer of each module is connected to the buffer of another module and/or the controller via data wiring for data transmission); and
wherein the second memory device receives the first write data from the second data buffer circuit (see Figs. 1-2 and paragraphs 212-213 and 235; the buffer 105 (i.e., second buffer 105 in memory module 103b) is provided with a DQ output driver 301 for outputting data to the DRAM 110, and a data receiver 302 for receiving read data from the DRAM 110).
With respect claim 3, Matsui teaches wherein: the primary interface of the first data buffer circuit is to couple to one of a group of links associated with the memory controller (see paragraphs 137-138; data wiring 111 is connected from the memory controller 101 to the buffer 105 of the memory module 103a).
With respect claim 4, Matsui teaches wherein: the memory module couples to the memory controller solely via the primary interface of the first data buffer circuit in a point-to-point configuration (see paragraph 147; data wiring 111 is connected point-to-point between the memory controller 101 and the memory module 103).
With respect claim 7, Matsui teaches wherein: the primary interface of the first data buffer circuit is to receive the first write data from the memory controller in accordance with a dynamic random access memory (DRAM) protocol (see paragraph 141; DRAM 110 is a DRAM of a x-8 configuration that can write and read data per 8 bits, data transmission/reception is performed on the unit of 8 bits).
With respect claim 8, Matsui teaches wherein: the primary interface of the first data buffer circuit is to operate at a first data rate (see paragraph 36 and 151; the data wiring 111 is fed with data and command/address signals at a transmission speed of 2.66 Gbps); and
the first secondary interface of the first data buffer circuit and the second secondary interface of the second data buffer circuit are to operate at a second data rate that is less than the first data rate (see paragraph 36 and 150-151; transmission speeds of the internal data wiring 111' is 1.33 Gbps).
With respect claim 9, Matsui teaches wherein: the second data rate comprises half the first data rate (see paragraphs 36 and 150-151; the data wiring 111 is fed with data and command/address signals at a transmission speed of 2.66 Gbps…transmission speeds of the internal data wiring 111' is 1.33 Gbps).
With respect claim 10, Matsui teaches buffering a first memory device and a second memory device from a memory controller (see Fig. 1 and paragraph 148; buffer 105 provided on each memory module 103a-103b has a function of receiving a data signal or a command/address signal from the memory controller 101), the buffering comprising
interfacing with a memory controller via a group of links coupled to a primary interface of a first data buffer circuit (see paragraphs 137-138; data wiring 111 is connected from the memory controller 101 to the buffer 105 of the memory module 103a. Also in paragraph 28; data is transmitted/received bidirectionally in the data wiring 111 between the controller and the buffer);
interfacing with the first memory device via a first secondary interface of the first data buffer circuit (see paragraph 140; the buffer 105 in each memory module 103 and the DRAMs 110 mounted in the subject memory module 103 are connected together via internal data wiring 111’) and the second memory device via a second secondary interface of a second data buffer circuit (see Figs. 1-2 and paragraph 140; the buffer 105 (i.e., buffer in module 103b) in each memory module 103 and the DRAMs 110 mounted in the subject memory module 103 are connected together via internal data wiring 111');
distributing first write data received at the primary interface of the first data buffer circuit, from the memory controller, to the second data buffer circuit (see paragraph 29; the buffer of each module is connected to the buffer of another module and/or the controller via data wiring for data transmission); and
transferring the first write data from the second secondary interface of the second data buffer circuit to the second memory device (see Figs. 1-2 and paragraphs 212-213 and 235; the buffer 105 (i.e., second buffer 105 in memory module 103b) is provided with a DQ output driver 301 for outputting data to the DRAM 110, and a data receiver 302 for receiving read data from the DRAM 110).
With respect claim 11, Matsui teaches wherein interfacing with the memory controller further comprises: coupling the primary interface of the first data buffer circuit to one of a group of links associated with the memory controller (see paragraphs 137-138; data wiring 111 is connected from the memory controller 101 to the buffer 105 of the memory module 103a).
With respect claim 12, Matsui teaches wherein interfacing with the memory controller comprises: coupling the memory module to the memory controller solely via the primary interface of the first data buffer circuit in a point-to-point configuration (see paragraph 147; data wiring 111 is connected point-to-point between the memory controller 101 and the memory module 103).
With respect claim 15, Matsui teaches wherein: receiving, with the primary interface of the first data buffer circuit, the first write data and the second write data from the memory controller comprises receiving the first write data and the second write data in accordance with a dynamic random access memory (DRAM) protocol (see paragraph 141; DRAM 110 is a DRAM of a x-8 configuration that can write and read data per 8 bits, data transmission/reception is performed on the unit of 8 bits).
With respect claim 16, Matsui teaches a first IC data buffer chip (see paragraph 176; buffer chips) comprising a primary interface (see paragraphs 137-138; data wiring 111 is connected from the memory controller 101 to the buffer 105 of the memory module 103a) to receive first write data from a memory controller (see paragraph 28; data is transmitted/received bidirectionally in the data wiring 111 between the controller and the buffer), the first IC data buffer chip comprising a first secondary interface coupled to a first memory device disposed on the memory module (see paragraph 140; the buffer 105 in each memory module 103 and the DRAMs 110 mounted in the subject memory module 103 are connected together via internal data wiring 111’);
a second IC data buffer chip (see paragraph 176; buffer chips) comprising a second secondary interface coupled to a second memory device disposed on the memory module (see Figs. 1-2 and paragraph 140; the buffer 105 (i.e., buffer in module 103b) in each memory module 103 and the DRAMs 110 mounted in the subject memory module 103 are connected together via internal data wiring 111'), the second IC data buffer chip coupled to the first IC data buffer chip via a data distribution path (see paragraph 19; buffers on the adjacent memory modules are connected to each other via data lines in a point-to-point fashion) and to receive the first write data via the data distribution path (see paragraph 29; the buffer of each module is connected to the buffer of another module and/or the controller via data wiring for data transmission); and
wherein the second secondary interface of the second IC data buffer chip is to transfer the first write data to the second memory device (see Figs. 1-2 and paragraphs 212-213 and 235; the buffer 105 (i.e., second buffer 105 in memory module 103b) is provided with a DQ output driver 301 for outputting data to the DRAM 110, and a data receiver 302 for receiving read data from the DRAM 110).
With respect claim 17, Matsui teaches wherein: solely the primary interface of the first IC data buffer chip is to couple to the memory controller in a point-to-point configuration (see paragraph 147; data wiring 111 is connected point-to-point between the memory controller 101 and the memory module 103); and
the second IC data buffer chip is to indirectly couple to the memory controller via the first IC data buffer chip (see paragraph 29; the buffer of each module is connected to the buffer of another module and/or the controller via data wiring for data transmission).
With respect claim 19, Matsui teaches wherein: the primary interface of the first IC data buffer chip is to receive the first write data from the memory controller in accordance with a dynamic random access memory (DRAM) protocol (see paragraph 141; DRAM 110 is a DRAM of a x-8 configuration that can write and read data per 8 bits, data transmission/reception is performed on the unit of 8 bits).
With respect claim 20, Matsui teaches wherein: the primary interface of the first IC data buffer chip is to operate at a first data rate (see paragraph 36 and 151; the data wiring 111 is fed with data and command/address signals at a transmission speed of 2.66 Gbps); and
the first secondary interface of the first IC data buffer chip and the second secondary interface of the second IC data buffer chip are to operate at a second data rate that is less than the first data rate (see paragraph 36 and 150-151; transmission speeds of the internal data wiring 111' is 1.33 Gbps).
With respect claim 21, Matsui teaches wherein: the second data rate comprises half the first data rate (see paragraphs 36 and 150-151; the data wiring 111 is fed with data and command/address signals at a transmission speed of 2.66 Gbps…transmission speeds of the internal data wiring 111' is 1.33 Gbps).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-6, 13-14 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsui (US2004/0105292) in view of Perego et al. (US2011/0219197).
With respect claim 5, Matsui teaches wherein: the primary interface of the first data buffer circuit is to receive second write data from the memory controller (see paragraph 28; data is transmitted/received bidirectionally in the data wiring 111 between the controller and the buffer).
Matsui does not teach wherein the first memory device is to receive the second write data from the first secondary interface of the first data buffer circuit concurrent with the second memory device receiving the first write data from the second secondary interface of the second data buffer circuit.
However, Perego et al. teaches wherein the CA1 or CA2 port may include two signal lines capable of carrying two bits of information in parallel…each memory device 1204 and 1206 may be independently accessed via the dedicated CA line (see pages 7-8, paragraph 93 and 94; and page 14, paragraph 162).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the module taught by Matsui to include the above mentioned to improve operation of the system (see Perego, page 2, paragraph 39, page 13, paragraph 144).
With respect claim 6, Matsui does not teach wherein: the first memory device is to receive the second write data during a first memory access time interval; and wherein the second memory device is to receive the first write data during a second memory access time interval that at least partially overlaps the first memory access time interval.
However, Perego et al. teaches wherein when the memory system 1200 is in the first operation mode, the controller logic 1222 generates the CA signals (CA1 and CA2) with a first signaling rate (e.g., 32 bits per one tRR interval, where tRR represents a minimum time interval between independent row accesses to a particular memory device). The CA1 or CA2 port may include multiple signal links capable of carrying multiple bits of information in parallel. In the example of FIG. 12, the CA1 or CA2 port may include two signal lines capable of carrying two bits of information in parallel, or the CA1 or CA2 port is two bits wide. So, when the CA signaling rate is 32 bits/ tRR, the CA1 or CA2 port may carry a maximum of 64 CA bits during one tRR interval or during 32 tBIT-CA intervals, wherein tBIT-CA represents a bit interval in a CA signal (see page 7, paragraph 93).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the module taught by Matsui to include the above mentioned to improve operation of the system (see Perego, page 2, paragraph 39, page 13, paragraph 144).
With respect claim 13, Matsui teaches receiving, with the primary interface of the first data buffer circuit, second write data from the memory controller (see paragraph 28; data is transmitted/received bidirectionally in the data wiring 111 between the controller and the buffer).
Matsui does not teach receiving, with the first memory device, the second write data from the first secondary interface of the first data buffer circuit concurrent with the second memory device receiving the first write data from the second secondary interface of the second data buffer circuit.
However, Perego et al. teaches wherein the CA1 or CA2 port may include two signal lines capable of carrying two bits of information in parallel…each memory device 1204 and 1206 may be independently accessed via the dedicated CA line (see pages 7-8, paragraph 93 and 94; and page 14, paragraph 162).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Matsui to include the above mentioned to improve operation of the system (see Perego, page 2, paragraph 39, page 13, paragraph 144).
With respect claim 14, Matsui does not teach receiving, with the first memory device, the second write data during a first memory access time interval; an receiving, with the second memory device, the first write data during a second memory access time interval that at least partially overlaps the first memory access time interval.
However, Perego et al. teaches wherein when the memory system 1200 is in the first operation mode, the controller logic 1222 generates the CA signals (CA1 and CA2) with a first signaling rate (e.g., 32 bits per one tRR interval, where tRR represents a minimum time interval between independent row accesses to a particular memory device). The CA1 or CA2 port may include multiple signal links capable of carrying multiple bits of information in parallel. In the example of FIG. 12, the CA1 or CA2 port may include two signal lines capable of carrying two bits of information in parallel, or the CA1 or CA2 port is two bits wide. So, when the CA signaling rate is 32 bits/ tRR, the CA1 or CA2 port may carry a maximum of 64 CA bits during one tRR interval or during 32 tBIT-CA intervals, wherein tBIT-CA represents a bit interval in a CA signal (see page 7, paragraph 93).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Matsui to include the above mentioned to improve operation of the system (see Perego, page 2, paragraph 39, page 13, paragraph 144).
With respect claim 18, Matsui teaches wherein: the primary interface of the first IC data buffer chip is to receive second write data from the memory controller (see paragraph 28; data is transmitted/received bidirectionally in the data wiring 111 between the controller and the buffer).
Matsui does not teach wherein the first IC data buffer chip is to transfer the second write data to the first memory device concurrent with the second IC data buffer chip transferring the first write data to the second memory device.
However, Perego et al. teaches wherein the CA1 or CA2 port may include two signal lines capable of carrying two bits of information in parallel…each memory device 1204 and 1206 may be independently accessed via the dedicated CA line (see pages 7-8, paragraph 93 and 94; and page 14, paragraph 162).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the circuit taught by Matsui to include the above mentioned to improve operation of the system (see Perego, page 2, paragraph 39, page 13, paragraph 144).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Halbert et al. (US 6,742,098) teaches dual-port buffer-to-memory interface.
Ware et al. (US2011/0016278) teaches independent threading of memory devices disposed on memory modules.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARACELIS RUIZ whose telephone number is (571)270-1038. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald G. Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ARACELIS RUIZ/Primary Examiner, Art Unit 2139