DETAILED ACTION
Claims 1-20 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
In the IDS submitted on June 22, 2026, the foreign documents have not been considered because copies of the documents have not been provided, as required by 37 CFR 1.98(a)(2). Applicant has provided machine translations and illegible drawings, but not copies of the documents per se.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not sufficiently descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. For now, the examiner recommends --Prefetching Data from a Load Target Address Determined by a PC-Relative Arithmetic Operation--.
Claim Objections/Recommendations
Claim 1, and similarly claims 15 and 20, are objected to because of the following informalities, taking claim 1 as representative:
In the 3rd to last line, delete “specified” for consistency with references to the same operation in the previous line and in line 9.
In claim 1, and similarly claims 15 and 20, instead of using “the result target address” at the end, the examiner recommends rewording the previous paragraph to say --in response to the detection, perform the PC-relative arithmetic operation, wherein the target address is a result of the PC-relative arithmetic operation; and--. Note that, if such a recommendation is accepted, “result” should be removed from claims 8-9, 12, and 18 as well.
Claim 7 is objected to because of the following informalities:
In line 6, there is a lack of antecedent basis for “the one or more instructions”, which could refer to the one or more instructions in line 3 or to those in claim 1, line 6. The examiner recommends inserting --second-- before “set” in line 3, and then inserting --second set of-- before “one” in line 6.
In lines 8-9, there is a lack of antecedent basis for “the specified PC-relative arithmetic operation” since there is such a specified operation in claim 1, and a second in claim 7, line 4. It appears that applicant should replace “specified” in line 8 with --second--.
In claim 7, instead of using “the result branch target address” at the end, the examiner recommends rewording the previous paragraph to say --perform the second PC-relative arithmetic operation, wherein the branch target address is a result of the second PC-relative arithmetic operation; and--.
Claim 10 is objected to because of the following informalities:
Please replace “operation” with --instruction--. Instructions are stored in instruction cache, not the operations caused by the instructions.
Claim 13 is objected to because of the following informalities:
In line 3, there is a lack of antecedent basis for “the prefetch request” because there is such a request in claim 1, line 4, and another in claim 12, line 3.
In claim 15, 4th to last line, the examiner recommends replacing “detection” with
--detecting--.
Claim 15 is objected to because of the following informalities:
In the 4th to last line, delete the space before the comma.
All claims are objected to due to their dependence on an objected-to claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-6, and 14-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yen et al. (US 2017/0046158).
Referring to claim 1, Yen has taught an apparatus, comprising:
processor circuitry (FIG.2, 201) configured to execute a load instruction to access data at a target address (from FIG.2 and paragraph 4, the LDR (load) instruction loads from multiple target addresses over time. The claimed target address maps to the second address in paragraph 4);
prefetch circuitry configured to generate a prefetch request to access data predicted to be utilized by the load instruction (from paragraphs 4 and 41-42, prefetch circuitry (FIG.2, at least 210+212) generates speculative prefetch requests based on various parameters to prefetch data predicted to be used by the load instruction), including to:
detect a set of one or more instructions, including the load instruction, that specify:
a program counter (PC)-relative arithmetic operation to determine the target address, wherein the PC-relative arithmetic operation depends on one or more immediate values in the one or more instructions (from FIG.2 and paragraphs 4 and 39-42, the prefetch circuitry detects the load instruction, which specifies that (causes) hash logic 210 is to perform PC-relative Boolean arithmetic (e.g. XOR) on data including a subset of the PC of the load instruction and an immediate value (#0x200) of the load instruction. The result of this hashing is used to lookup information used to generate a target address of the load instruction. Thus, the claimed operation is mapped to a combination of the arithmetic, table lookup, and generation of a target address based on the table lookup); and
a load operation to the target address (again, see paragraphs 4 an d39-42. The detected load will cause a load operation to the target address generated based on table 212 lookup);
in response to the detection, perform the PC-relative arithmetic operation to determine a target address for the load operation (again, from FIG.2 and paragraphs 39-42, in response to the load instruction, the operation is actually performed and the result, i.e., the address generated based on hash calculation and table lookup, is the target address); and
initiate a data prefetch to the result target address (again, from the citations above, once the target for the load instruction is determined as a result of the operation, a prefetch is initiated).
Referring to claim 2, Yen has taught the apparatus of claim 1, wherein the detection includes to: detect a multiple-instruction pattern that specifies the PC-relative arithmetic operation and the load operation; and wherein the prefetch circuitry is configured to perform the PC-relative arithmetic operation and initiate the data prefetch in response to detection of the pattern (a load instruction is a multiple-instruction pattern because any load may be executed multiple times and make use of prefetching. As such, when a load, which specifies the arithmetic operation and load operation are to occur, the operation is performed to initiate the prefetch).
Referring to claim 4, Yen has taught the apparatus of claim 2, further comprising:
an instruction cache (see paragraph 25);
wherein the detection of the multiple-instruction pattern is performed within a set of instructions for a fill operation to the instruction cache (an instruction cache is filled with instructions. Loads fetched from instruction cache at 202 would then be detected. Thus, the detection is performed among a set of instructions that filled an instruction cache).
Referring to claim 5, Yen has taught the apparatus of claim 4, wherein the detection of the multiple-instruction pattern is performed across multiple beats of instructions for the fill operation and includes to store state information relating to one or more non-final beats of the beats of instructions (the detection is part of the system (FIG.2), meaning loads filled into the cache over time (as part of beats/chunks) will be detected. Prefetch table 212 stores data for various loads in various beats).
Referring to claim 6, Yen has taught the apparatus of claim 4, wherein the prefetch circuitry is configured to perform the detection of the multiple-instruction stream pattern, the PC-relative arithmetic operation, and initiation of a data prefetch for multiple multiple-instruction patterns within the set of instructions for the fill operation (again, the prefetch circuitry performs these operations over time for various loads as part of the design (FIG.2). As such, multiple multi-load patterns are detected).
Referring to claim 14, Yen has taught the apparatus of claim 1, wherein the apparatus is a computing device that further comprises: a display (FIG.4, 428); a central processing unit (FIG.4, 201); and a network interface (FIG.4, 440, which may be a modem (paragraph 48)).
Claims 15-17 are rejected for similar reasoning as claim 1-2 and 4, respectively.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yen in view of Hirotsu et al. (US 2012/0173850) and the examiner’s taking of Official Notice.
Referring to claim 7, Yen has taught the apparatus of claim 1, but has not taught wherein the prefetch circuitry is further configured to: detect a set of one or more instructions that specify: a second PC-relative arithmetic operation to determine a branch target address, wherein the second PC-relative arithmetic operation depends on one or more immediate values in the one or more instructions; and a branch operation to the branch target address; perform the second PC-relative arithmetic operation, wherein a result of the specified PC-relative arithmetic operation is the branch target address; and initiate an instruction prefetch to the result branch target address. However, Hirotsu has taught prefetch circuitry that detects whether stored instructions include a branch and an instruction for calculating the target address of the branch, and, if so, the address is calculated and a prefetch request is generated to store the prefetched target into cache (see claim 4). Further, Official Notice is taken that calculating a branch address based on adding an immediate value to a program counter value was well known in the art before applicant’s invention. Such allows to quickly determine the address because the offset does not need to be fetched from another location, and also because another location does not need to be consumed (since the offset is in the instruction itself). This combination of teachings would allow Yen to extend prefetching to branch instructions, thereby allowing for faster access to the target branch path. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yen such that the prefetch circuitry is further configured to: detect a set of one or more instructions that specify: a second PC-relative arithmetic operation to determine a branch target address, wherein the second PC-relative arithmetic operation depends on one or more immediate values in the one or more instructions; and a branch operation to the branch target address; perform the second PC-relative arithmetic operation, wherein a result of the specified PC-relative arithmetic operation is the branch target address; and initiate an instruction prefetch to the result branch target address.
Claims 8-9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Yen in view of Weinberger et al. (US 6,453,389).
Referring to claim 8, Yen has taught the apparatus of claim 1, but has not taught wherein the prefetch circuitry is further configured to: check that the result target address is not already resident in a prefetch queue prior to initiating the data prefetch to the result target address. However, Weinberger has taught, in column 6, lines 7-25, that a prefetch request is only added to a queue if the same request is not already in the queue. This ensures that redundant prefetches are not performed. A queue also allows prefetches to be built up if they cannot be performed as fast as the need for them is detected. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yen such that the prefetch circuitry is further configured to: check that the result target address is not already resident in a prefetch queue prior to initiating the data prefetch to the result target address.
Referring to claim 9, Yen, as modified, has taught the apparatus of claim 8, further comprising: load circuitry configured to check for a hit in a data cache prior to performing the data prefetch to the result target address, wherein the data prefetch is into the data cache (Weinberger not only checks to see if the prefetch request is already in the queue, but also checks if the data to be prefetched is already in the cache (column 6, lines 7-25). In either case, time would be saved by not redundantly performing a prefetch).
Claim 18 is rejected for similar reasoning as claim 9.
Claims 10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yen.
Referring to claim 10, Yen has taught the apparatus of claim 1, but has not taught circuitry configured to perform the data prefetch prior to fetch of the load operation from an instruction cache. However, recall that the prefetch occurs for the second load operation, after the first load operation is fetched from cache (FIG.2 and paragraph 25). While Yen has not taught that this prefetch occurs before the load instruction is fetched a second time to perform the second load operation, the examiner asserts that one of ordinary skill in the art would have recognized that the second load operation could occur at any point in the program with respect to the first load operation. This is dependent on the program and when the programmer desires for loads to occur. The advantage of having the loads sufficiently spaced out is it increases the chance of the prefetched data being available in time for the second load operation to be performed. As such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yen to include circuitry configured to perform the data prefetch prior to fetch of the load instruction a second time to perform the load operation from an instruction cache.
Claim 19 is rejected for similar reasoning as claim 10.
Claims 11 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yen in view of the examiner’s taking of Official Notice.
Referring to claim 11, Yen has taught the apparatus of claim 1, wherein the prefetch circuitry includes an adder dedicated to perform the PC-relative arithmetic operation for prefetches (as discussed above, the adder includes XOR circuitry to perform XOR which adds bits together without a carry (this is a form of Boolean addition)). Yen has not taught that the address is a single-cycle adder. However, Official Notice is taken that single-cycle XOR was well known in the art before applicant’s invention. Such allows for minimal time spent performing the operation, which speeds up the system. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yen such that the adder is a single-cycle adder.
Claim 20 is mostly rejected for similar reasoning as claim 1. Yen has not taught a non-transitory computer-readable medium having instructions of a hardware description programming language stored thereon that, when processed by a processor, program the processor to generate a computer simulation model, wherein the model represents a hardware circuit that includes the claimed processor circuitry and prefetch circuitry. However, Official Notice is taken that storing HDL code to generate a simulation model was well known in the art before applicant’s invention. Such allows for a software implementation of a design for testing and debugging without physically building the hardware system. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yen to include a non-transitory computer-readable medium having instructions of a hardware description programming language stored thereon that, when processed by a processor, program the processor to generate a computer simulation model, wherein the model represents a hardware circuit that includes the claimed processor circuitry and prefetch circuitry.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Yen in view of Gelman (US 2002/0174303).
Referring to claim 12, Yen has taught the apparatus of claim 1, but has not taught wherein: to initiate the data prefetch to the result target address, the prefetch circuitry is configured to send a prefetch request to a prefetch queue; and the prefetch circuitry is configured to flush the prefetch queue in response to one or more flush events. However, Gelman has taught a prefetch queue to queue prefetch requests, and also to flush the prefetch queue when a branch misprediction occurs (see paragraph 37). A queue is useful to allow prefetches to be built up if they cannot be performed as fast as the need for them is detected (e.g. if the prefetch table is requesting prefetches at a higher frequency than existing prefetches are completing). Additionally, flushing the queue is useful to not perform prefetches for instructions that are not executed since they are on an incorrectly predicted branch path. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yen such that to initiate the data prefetch to the result target address, the prefetch circuitry is configured to send a prefetch request to a prefetch queue; and the prefetch circuitry is configured to flush the prefetch queue in response to one or more flush events.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Yen in view of Gelman and the examiner’s taking of Official Notice.
Referring to claim 13, Yen, as modified, has taught the apparatus of claim 12, but has not taught wherein the apparatus further includes credit circuitry configured to determine whether the prefetch queue is in a state that allows acceptance of the prefetch request based on tracking credits for the prefetch queue. However, Official Notice is taken that tracking the fullness of a queue based on a counter (credit tracker) was well known in the art before applicant’s invention. A queue has a finite number of entries and as long as there are empty entries (i.e., credit), more prefetch requests could be queued. However, if the queue is full, a new request could not be stored unless a previous request is overwritten. Thus, in order to prevent deletion of a previous request, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yen such that the apparatus further includes credit circuitry configured to determine whether the prefetch queue is in a state that allows acceptance of the prefetch request based on tracking credits for the prefetch queue.
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
On pages 9-10 of applicant’s response, applicant argues that Yen’s unique identifier does not correspond to a target address of the load instruction.
The examiner respectfully disagrees. The arithmetic operation (hashing+lookup+target address generation) does correspond to a target address of the load instruction. It corresponds to the next target address of the load instruction. In other words, a load instruction generates an identifier to prefetch from a target address for a future occurrence of the load instruction.
On page 10 of applicant’s response, applicant argues that Yen’s LDR instruction uses register+offset encoding to specify a target address and does not specify a PC-relative arithmetic operation to determine the target address.
This is not persuasive. The load instruction has multiple target addresses over time that may differ based on some stride for instance, and, thus, are predictable. While register+offset determines a target address for the LDR already in the pipeline, the arithmetic operation performed as a result of the LDR in the pipeline determines the next target address of the same instruction. The claim reads on this operation.
On page 10 of applicant’s response, applicant argues that the result of Yen’s hash encoding is an instruction identifier, not the target address.
The examiner asserts that applicant is interpreting the claimed arithmetic operation too narrowly. The examiner is interpreting PC-relative arithmetic operation to include the hashing 210 (which is PC-relative), the lookup in table 212, and the generation of the target address based on information retrieved based on the lookup in table 212. All of these collectively form an operation, which is based on PC-relative arithmetic performed during the hashing operation.
On page 11 of applicant’s response, applicant argues the use of Official Notice, stating that, if the Official Notice is correct, it should be a trivial matter for the examiner to cite supporting references.
The examiner agrees and notes that references are cited upon applicant’s submission of an adequate traversal, which would include stating why the noticed features are not well known in the art. Note that an inadequate traversal results in the common knowledge becoming admitted prior art. See MPEP 2144.03(C).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183
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