DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
Paragraph [0035], lines 6-7, should read as, “And in the thirteenth loop Loop13 to the fifteenth loop Loop15 that are performed after the program is completed, . . .”
Para. [0018] should read as, “ FIG. 9 is an example graph showing why the start loop in which the program bit line voltage described in FIG. 3 is applied must be before the loop in which the verification operation begins.”
Para. [0100], lines 1-5, should read as, “FIG. 9 is an example graph showing why the start loop in which the program bit line voltage described in FIG. 3 is applied must be before the loop in which the verification operation begins. A method in which the starting loop to which the program bit line voltage Vblpgm is applied is before the loop to which the verification operation starts is hereinafter referred to as the preceding program bit line PPBL.”
Appropriate correction is required.
Claim Objections
Claims 3, 9, and 11 objected to because of the following informalities:
Claim 3, should read as, “The method of claim 2, wherein a plurality of bit lines of a second plurality of memory cells programmed to the lowest program state receive the program bit line voltage during the first program loop.”
Claim 9, line 8, should read as, “control the page buffer and to provide . . .” because the following limitations involve bit line voltage settings and do not involve the word lines.
Claim 11, line 2, should read as, “. . . to provide the program bit line voltage during a first program loop to a plurality of bit lines . . .”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites, “executing a first program loop, wherein in the first program loop a first program voltage is applied to a word line based on a plurality of bit lines of a first plurality of memory cells being set to an inhibitory bit line voltage, the first plurality of memory cells programmed to a first target state; and after executing the first program loop, executing a second program loop, wherein in the second program loop a second program voltage is applied to the word line based on the plurality of bit lines of the first plurality of memory cells being set to a program bit line voltage.” (emphasis added).
FIGs. 13 and 17 illustrate two scenarios for defining waveforms of programming voltages (Vpgm) applied to word lines during each programming loop. Accordingly, FIG. 13 demonstrates a variable voltage offset (∆Vi, ‘i” is the loop count) for reducing amplitudes of programming voltages (Vpgm) based on the programming loop count (see paras. [0116-0117]); and FIG. 17 demonstrates a variable pulse width offset (∆Wi, ‘i’ is the loop count) for reducing pulse widths of programming voltages (Vpgm) based on the programming loop count (see paras. [0129-0130])—not a voltage status of a plurality of bit lines (i.e., the number of bit lines set to an inhibitory bit line voltage or the number of bit lines set to a program bit line voltage).
Additionally, reciting “the first plurality of memory cells programmed to a first target state” within the limitation of “executing a first program loop” expresses the first plurality of memory cells may be paradoxically programmed in the first program loop, or perhaps prior, when the corresponding plurality of bit lines is set to an inhibitory bit line voltage. The first plurality of memory cells are not programmed when their bit lines are set to an inhibitory bit line voltage. The first plurality of memory cells must be programmed to the first target state in either the second program loop or a following programming loop when the corresponding bit lines are set to a program bit line voltage (e.g., FIG. 3: “the first plurality of memory cells” maps to the memory cells programmed to states P2 to P7)
Claims 2-8 are rejected because the depend on claim 1; therefore, claims 2-8 contain at least the same defect(s).
Claim 4 recites, “a third program voltage is applied to the word line based on the plurality of bit lines of the first plurality of memory cells being set to the program bit line voltage, . . .” (emphasis added). FIG. 13 demonstrates a variable voltage offset (∆Vi, ‘i” is the loop count) for reducing amplitudes of programming voltages (Vpgm) based on the programming loop count (see paras. [0116-0117]); and FIG. 17 demonstrates a variable pulse width offset (∆Wi, ‘i’ is the loop count) for reducing pulse widths of programming voltages (Vpgm) based on the programming loop count (see paras. [0129-0130]).
Claim 5 is rejected because the depend on claim 4; therefore, claim 5 contains at least the same defect(s).
Claim 5 recites, “a plurality of bit lines of a third plurality of memory cells in the second program loop are set to the inhibitory bit line voltage, the third plurality of memory cells being programmed to a second target state higher than the first target state.” (emphasis added). The third plurality of memory cells are not programmed when their bit lines are set to an inhibitory bit line voltage. The third plurality of memory cells must be programmed to the second target state in a programming loop following the second programming loop when the corresponding bit lines are set to a program bit line voltage (e.g., FIG. 3: “the third plurality of memory cells” maps to memory cells programmed to states P3 to P7)
Claim 9 recites, “a control circuit configured to control the page buffer and the row decoder to provide an inhibit bit line voltage to a plurality of bit lines of a first plurality of memory cells during an inhibit loop period . . . the inhibit loop period including an initial program loop of the first plurality of memory cells programmed to a first target state.” The first plurality of memory cells are not programmed when their bit lines are set to an inhibitory bit line voltage.
Claims 10-15 are rejected because the depend on claim 9; therefore, claims 10-15 contain at least the same defect(s).
Claim 16 recites, “a plurality of bit lines of a plurality of memory cells is set to an inhibitory bit line voltage during a first loop period, the plurality of memory cells programmed to a first target state.” (emphasis added). The plurality of memory cells are not programmed when their bit lines are set to an inhibitory bit line voltage in the first loop period. The plurality of memory cells must be programmed to the first target state in a programming loop following the first loop period, in the second loop period, when the corresponding bit lines are set to a program bit line voltage (e.g., FIG. 3: “the plurality of memory cells” maps to memory cells programmed to states P2 to P7).
Claims 17-20 are rejected because the depend on claim 16; therefore, claims 17-20 contain at least the same defect(s).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 9-11, and 16-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Maijima et al (US 20170178739 A1; hereinafter "Maejima").
Regarding claim 1, Maejima discloses:
A method of programming a non-volatile memory device for programming memory cells with a plurality of target states (FIG. 25 is a diagram showing a relationship between the number of loops and a bit line voltage during a writing operation of the semiconductor memory device; FIG. 4 is a graph showing distribution of threshold voltage values of a memory cell transistor according to the first embodiment), comprising:
executing a first program loop, wherein in the first program loop a first program voltage is applied to a word line based on a plurality of bit lines of a first plurality of memory cells being set to an inhibitory bit line voltage, (FIG. 25 and para. [0166]: “the bit lines BL (“B”), BL (“C”), BL (“D”), BL (“E”), BL (“F”), and BL (“G”) that are set as targets for ‘0’ [sic] writing in the first to sixth loops in FIG. 24 are inhibited from writing.”—‘0’ should be ‘1’; para. [0071]; “an operation of maintaining a threshold voltage value is referred to as “‘1’ programming”, “‘1’ writing”, or “writing inhibition”, and a bit line BL which is a target for ‘1’ programming is given ‘1’ data.”)
the first plurality of memory cells programmed to a first target state (FIG. 25: programming levels “B” through “G”); and
after executing the first program loop, executing a second program loop, wherein in the second program loop a second program voltage is applied to the word line based on the plurality of bit lines of the first plurality of memory cells being set to a program bit line voltage (FIGs. 9 and 10 illustrated word line programming voltages VPGM in each programming loop; FIG. 25: bit lines associated with a “B” level are inhibited in loop 2 and then program enabled in loops 3-8).
Regarding claim 2, Maejima discloses:
the first target state corresponds to any one of the plurality of target states excluding an erase state and a lowest program state (FIG. 25: “Er” level is inhibited throughout each programming loop and “A” level may be enabled in loops 1-6).
Regarding claim 3, Maejima discloses:
a second plurality of memory cells programmed to the lowest program state receive the program bit line voltage from the first program loop (FIG. 25: “A” level may be enabled in loops 1-6).
Regarding claim 9, Maejima discloses:
A non-volatile memory device (FIG. 1: NAND-type flash memory 1), comprising:
a cell array including a plurality of memory cells connected to a plurality of bit lines (FIG. 1: memory array 2; FIG. 2 and para. [0052]: bit lines BL0 to BL(L-1));
a row decoder configured to transfer a program voltage or a pass voltage to a plurality of word lines of the plurality of memory cells during a program operation (para. [0079]: “the row decoder 3 selects any of the word lines WL in the selected block BLK, applies a voltage VPGM to the selected word line, and applies a voltage VPASS to the other non-selected word lines WL.”);
a page buffer configured to set the plurality of bit lines to a program bit line voltage or an inhibitory bit line voltage (para. [0074]: “the sense amplifier 4 transmits programming data to each bit line BL. An “L” level, for example, 0 V is applied to a bit line BL given ‘0’ data. An “H” level, for example, 2.5 V is applied to a bit line BL given ‘1’ data.”); and
a control circuit (FIG. 1: control circuit 5) configured to control the page buffer and the row decoder to provide an inhibit bit line voltage to a plurality of bit lines of a first plurality of memory cells during an inhibit loop period (FIG. 25 and para. [0166]: “the bit lines BL (“B”), BL (“C”), BL (“D”), BL (“E”), BL (“F”), and BL (“G”) that are set as targets for ‘0’ [sic] writing in the first to sixth loops in FIG. 24 are inhibited from writing.”—‘0’ should be ‘1’; para. [0071]; “an operation of maintaining a threshold voltage value is referred to as “‘1’ programming”, “‘1’ writing”, or “writing inhibition”, and a bit line BL which is a target for ‘1’ programming is given ‘1’ data.”), and
to provide the program bit line voltage to the plurality of bit lines of the first plurality of memory cells during a program loop period following the inhibit loop period, the inhibit loop period including an initial program loop of the first plurality of memory cells programmed to a first target state (FIGs. 9 and 10 illustrated word line programming voltages VPGM in each programming loop; FIG. 25: bit lines associated with a “A “ level may not be inhibited in loop 1; bit lines associated with a “B” level are inhibited in loops 1-2 and then program enabled in loops 3-8).
Regarding claim 10, Maejima discloses:
the first target state corresponds to any one program state other than an erase state and a lowest program state among a plurality of program states (FIG. 25: “Er” level is inhibited throughout each programming loop and “A” level may be enabled in loops 1-6).
Regarding claim 11, Maejima discloses:
the control circuit is configured to control the page buffer to provide the program bit line voltage from a first program loop to a plurality of bit lines of a second plurality of memory cells, the second plurality of memory cells being programmed to the lowest program state (FIG. 25: “A” level may be enabled in loops 1-6).
Regarding claim 16, Maejima discloses:
A method of programming a non-volatile memory device (FIG. 1: NAND-type flash memory 1) for programming selected memory cells to a plurality of target states (FIG. 25 is a diagram showing a relationship between the number of loops and a bit line voltage during a writing operation of the semiconductor memory device; FIG. 4 is a graph showing distribution of threshold voltage values of a memory cell transistor according to the first embodiment), the method comprising:
executing at least one program loop, wherein a plurality of bit lines of a plurality of memory cells is set to an inhibitory bit line voltage during a first loop period (FIG. 25 and para. [0166]: “the bit lines BL (“B”), BL (“C”), BL (“D”), BL (“E”), BL (“F”), and BL (“G”) that are set as targets for ‘0’ [sic] writing in the first to sixth loops in FIG. 24 are inhibited from writing.”—‘0’ should be ‘1’; para. [0071]; “an operation of maintaining a threshold voltage value is referred to as “‘1’ programming”, “‘1’ writing”, or “writing inhibition”, and a bit line BL which is a target for ‘1’ programming is given ‘1’ data.”),
the plurality of memory cells programmed to a first target state (FIG. 25: programming levels “B” through “G”); and
executing a plurality of program loops, wherein the plurality of bit lines of the plurality of memory cells is set to a program bit line voltage during a second loop period following the first loop period (FIGs. 9 and 10 illustrated word line programming voltages VPGM in each programming loop; FIG. 25: bit lines associated with a “B” level are inhibited in loop 2 and then program enabled in loops 3-8).
Regarding claim 17, Maejima discloses:
the at least one program loop includes a program start loop (FIG. 25: for “A” level, loop 1; for “B” level, loop 3; for “C” level, loop 5; and so on).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUSTIN BRYCE HEISTERKAMP whose telephone number is (703)756-1095. The examiner can normally be reached M-F 0800-1700.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUSTIN BRYCE HEISTERKAMP/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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