Prosecution Insights
Last updated: October 27, 2026
Application No. 19/019,309

FAULT MANAGED POWER SYSTEMS

Non-Final OA §DOUBLEPATENT
Filed
Jan 13, 2025
Priority
Oct 13, 2020 — provisional 63/090,845 +3 more
Examiner
PATEL, DHARTI HARIDAS
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Schneider Electric SE
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
6m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
1111 granted / 1272 resolved
+19.3% vs TC avg
Moderate +8% lift
Without
With
+7.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
23 currently pending
Career history
1295
Total Applications
across all art units

Statute-Specific Performance

§101
1.0%
-39.0% vs TC avg
§103
42.8%
+2.8% vs TC avg
§102
44.2%
+4.2% vs TC avg
§112
2.5%
-37.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1272 resolved cases

Office Action

§DOUBLEPATENT
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-24 of U.S. Patent No. 12,248,032. Although the claims at issue are not identical, they are not patentably distinct from each other. The claims of the current application are broader than the patented claims. The patented claims disclose all the claim limitations of the current application as follows. Current Application: 19/019,309 U. S. Patent: 12,248,032 A fault managed power system (FMPS) configured to provide at least 100 Watts of power, the FMPS comprising: a receiver including a DC/DC converter and a receiver switch that is configured to provide to the DC/DC converter a series of current pulses that would not result in a person going into ventricular fibrillation from an electrical shock; and a source controller connected to the receiver by a pair of electrical conductors, the source controller including a source switch configured to connect electrical power from a power source to the pair of electrical conductors, wherein the source controller is configured to determine whether a leakage current is present on either or both of the electrical conductors during a current-off interval of the series of current pulses, the leakage current being greater than a predetermined current threshold on either or both of the electrical conductors, and wherein the source controller is further configured to control the source switch to disconnect the power source from the electrical conductors in response to determining that the leakage current is present on either or both of the electrical conductors during the current-off interval of the series of current pulses. 1. A fault managed power system operable to provide at least 100 Watts of power, comprising: a receiver including a DC/DC converter and a receiver switch controllable to provide a series of current pulses to the DC/DC converter at a predefined rate such that the current pulses are below a level that would result in a person going into ventricular fibrillation from an electrical shock; a source controller connected to the receiver by a pair of electrical conductors, the source controller including a source switch controllable to connect electrical power from a power source to the pair of electrical conductors; and a gate controller at the source controller, the gate controller programmed to determine whether a leakage current is present on either or both of the electrical conductors during a current-off interval of the series of current pulses, the leakage current being greater than a predetermined current threshold on either or both of the electrical conductors; wherein the gate controller is further programmed to control the source switch to disconnect the power source from the electrical conductors in response to determining that the leakage current is present on either or both of the electrical conductors during the current-off interval of the series of current pulses. 2. The FMPS of claim 1, wherein the receiver switch or the source switch, or both, is a high-power N-channel enhancement mode SiC MOSFET or a Si MOSFET switch. 2. The fault managed power system of claim 1, wherein the receiver switch or the source switch, or both, is a high-power N-channel enhancement mode SiC MOSFET or a Si MOSFET switch. 3. The FMPS of claim 1, wherein the source controller is configured to determine whether the leakage current is present on either or both of the electrical conductors using at least one leakage current detector at the source controller, the at least one leakage current detector deployed on either or both of the electrical conductors. 3. The fault managed power system of claim 1, wherein the gate controller is programmed to determine whether the leakage current is present on either or both of the electrical conductors using at least one leakage current detector at the source controller, the at least one leakage current detector deployed on either or both of the electrical conductors. 4. The FMPS of claim 3, wherein each leakage current detector includes an operational amplifier having input terminals that are connected in line with one of the electrical conductors and a leakage sensing resistor connected across the input terminals, the leakage sensing resistor having a sufficiently large resistance to cause a measurable voltage drop across the input terminals of the operational amplifier in the presence of the leakage current. 4. The fault managed power system of claim 3, wherein each leakage current detector includes an operational amplifier having input terminals that are connected in line with one of the electrical conductors and a leakage sensing resistor connected across the input terminals, the leakage sensing resistor having a sufficiently large resistance to cause a measurable voltage drop across the input terminals of the operational amplifier in the presence of the leakage current. 5. The FMPS of claim 4, wherein each leakage current detector further includes a leakage current switch connected across the input terminals of the operational amplifier, the leakage current switch controllable to route current from one of the electrical conductors through the leakage sensing resistor during the current-off interval of the series of current pulses. 5. The fault managed power system of claim 4, wherein each leakage current detector further includes a leakage current switch connected across the input terminals of the operational amplifier, the leakage current switch controllable to route current from one of the electrical conductors through the leakage sensing resistor during the current-off interval of the series of current pulses. 6. The FMPS of claim 1, further comprising at least one current sensor at the source controller, the at least one current sensor deployed on either or both of the electrical conductors, wherein the source controller is further configured to determine whether current pulses are present on either or both of the electrical conductors during a current-on interval of the series of current pulses using the at least one current sensor. 6. The fault managed power system of claim 1, further comprising at least one current sensor at the source controller, the at least one current sensor deployed on either or both of the electrical conductors, wherein the gate controller is further programmed to determine whether current pulses are present on either or both of the electrical conductors during a current-on interval of the series of current pulses using the at least one current sensor. 7. The FMPS of claim 6, wherein the source controller is further configured to determine whether a short-circuit condition or an overload condition is present on either or both of the electrical conductors using the at least one current sensor. 7. The fault managed power system of claim 6, wherein the gate controller is further programmed to determine whether a short-circuit condition or an overload condition is present on either or both of the electrical conductors using the at least one current sensor. 8. The FMPS of claim 1, wherein the source controller is further configured to determine whether a predetermined number of confirmation current pulses are present on either or both of the electrical conductors after a receiver charging current has been applied to the receiver. 8. The fault managed power system of claim 1, wherein the gate controller is further programmed to determine whether a predetermined number of confirmation current pulses are present on either or both of the electrical conductors after a receiver charging current has been applied to the receiver. 9. The FMPS of claim 8, wherein the receiver includes a bootstrap circuit comprising a linear regulating transistor and a voltage limiting capacitor configured to initially apply the receiver charging current to the receiver, and subsequently apply a full current to the receiver. 9. The fault managed power system of claim 8, wherein the receiver includes a bootstrap circuit comprising a linear regulating transistor and a voltage limiting capacitor configured to initially apply the receiver charging current to the receiver, and subsequently apply a full current to the receiver. 10. A method of managing fault in a power system operable to provide at least 100 Watts of power, the method comprising: connecting, at a source controller, electrical power from a power source to a pair of electrical conductors; receiving, at a receiver, electrical power from the power source on the pair of electric conductors connected to the receiver; providing, at the receiver, a series of current pulses to a DC/DC converter that would not result in a person going into ventricular fibrillation from an electrical shock; determining, at the source controller, whether a leakage current is present on either or both of the electrical conductors during a current-off interval of the series of current pulses, the leakage current being greater than a preset current threshold on either or both of the electrical conductors; and disconnecting, at the source controller, the power source from the electrical conductors in response to determining that the leakage current is present on either or both of the electrical conductors during the current-off interval of the series of current pulses. 10. A method of managing fault in a power system operable to provide at least 100 Watts of power, comprising: connecting, at a source controller, electrical power from a power source to a pair of electrical conductors; receiving, at a receiver, electrical power from the power source on the pair of electric conductors connected to the receiver; providing, at the receiver, a series of current pulses to a DC/DC converter at a predefined rate such that the current pulses are below a level that would result in a person going into ventricular fibrillation from an electrical shock; determining, at the source controller, whether a leakage current is present on either or both of the electrical conductors during a current-off interval of the series of current pulses, the leakage current being greater than a preset current threshold on either or both of the electrical conductors; and disconnecting, at the source controller, the power source from the electrical conductors in response to determining that the leakage current is present on either or both of the electrical conductors during the current-off interval of the series of current pulses. 11. The method of claim 10, wherein electrical power from the power source is connected to the electrical conductors using a high-power N-channel enhancement mode SiC MOSFET switch, or wherein the series of current pulses is provided to the DC/DC converter using a high-power N-channel enhancement mode SiC MOSFET switch or a Si MOSFET. 11. The method of claim 10, wherein electrical power from the power source is connected to the electrical conductors using a high-power N-channel enhancement mode SiC MOSFET switch, or wherein the series of current pulses is provided to the DC/DC converter using a high-power N-channel enhancement mode SiC MOSFET switch or a Si MOSFET. 12. The method of claim 10, wherein determining whether the leakage current is present on either or both of the electrical conductors is performed using at least one leakage current detector at the source controller, the at least one leakage current detector deployed on either or both of the electrical conductors. 12. The method of claim 10, wherein determining whether the leakage current is present on either or both of the electrical conductors is performed using at least one leakage current detector at the source controller, the at least one leakage current detector deployed on either or both of the electrical conductors. 13. The method of claim 12, wherein each leakage current detector includes an operational amplifier having input terminals that are connected in line with one of the electrical conductors and a leakage sensing resistor connected across the input terminals, the leakage sensing resistor having a sufficiently large resistance to cause a measurable voltage drop across the input terminals of the operational amplifier in the presence of the leakage current. 13. The method of claim 12, wherein each leakage current detector includes an operational amplifier having input terminals that are connected in line with one of the electrical conductors and a leakage sensing resistor connected across the input terminals, the leakage sensing resistor having a sufficiently large resistance to cause a measurable voltage drop across the input terminals of the operational amplifier in the presence of the leakage current. 14. The method of claim 13, wherein each leakage current detector further includes a leakage current switch connected across the input terminals of the operational amplifier, the leakage current switch controllable to route current from one of the electrical conductors through the leakage sensing resistor during the current-off interval of the series of current pulses. 14. The method of claim 13, wherein each leakage current detector further includes a leakage current switch connected across the input terminals of the operational amplifier, the leakage current switch controllable to route current from one of the electrical conductors through the leakage sensing resistor during the current-off interval of the series of current pulses. 15. The method of claim 10, further comprising determining, at the source controller, whether current pulses are present on either or both of the electrical conductors during a current-on interval of the series of current pulses, by using at least one current sensor at the source controller, the at least one current sensor deployed on either or both of the electrical conductors. 15. The method of claim 10, further comprising determining, at the source controller, whether current pulses are present on either or both of the electrical conductors during a current-on interval of the series of current pulses, by using at least one current sensor at the source controller, the at least one current sensor deployed on either or both of the electrical conductors. 16. The method of claim 15, further comprising determining whether a short-circuit condition or an overload condition is present on either or both of the electrical conductors using the at least one current sensor. 16. The method of claim 15, further comprising determining whether a short-circuit condition or an overload condition is present on either or both of the electrical conductors using the at least one current sensor. 17. The method of claim 10, further comprising determining, at the source controller, whether a predetermined number of confirmation current pulses are present on either or both of the electrical conductors after a receiver charging current has been applied to the receiver. 17. The method of claim 10, further comprising determining, at the source controller, whether a predetermined number of confirmation current pulses are present on either or both of the electrical conductors after a receiver charging current has been applied to the receiver. 18. The method of claim 17, further comprising initially applying the receiver charging current to the receiver and subsequently applying a full current to the receiver using a bootstrap circuit in the receiver, the bootstrap circuit including a linear regulating transistor and a voltage limiting capacitor. 18. The method of claim 17, further comprising initially applying the receiver charging current to the receiver and subsequently applying a full current to the receiver using a bootstrap circuit in the receiver, the bootstrap circuit including a linear regulating transistor and a voltage limiting capacitor. 19. A fault managed power system (FMPS) that is configured to provide a series of current pulses having a current level that does not exceed a touch-safe level on at least one cable, the FMPS being further configured to provide at least 100 Watts of power to a plurality of devices connected to the at least one cable; wherein the FMPS is further configured to determine whether a leakage current is present on the at least one cable during a current-off interval of the series of current pulses, the leakage current being greater than a predetermined threshold current on the at least one cable. 19. A network of powered devices, comprising: at least one network cable; a fault managed power system connected to the at least one network cable and providing configured to provide a series of current pulses having a current level that is below a touch-safe level on the at least one network cable, the managed power system operable to provide at least 100 Watts of power; and a plurality of powered devices connected to the at least one network cable and the fault managed power system, each powered device configured to be powered by electrical power from the fault managed power system; wherein the fault managed power system is further operable to determine whether a leakage current is present on the at least one network cable during a current-off interval of the series of current pulses, the leakage current being greater than a predetermined threshold current on the at least one network cable. 20. The FMPS of claim 19, wherein the at least one cable is a powered fiber cable or a twisted-pair cable. 21. The network of claim 19, wherein the at least one network cable is a powered fiber cable and electrical power is transmitted over an electrical conductor in the powered fiber cable while network data is transmitted over an optical conductor in the powered fiber cable. 22. The network of claim 19, wherein the at least one network cable is a twisted-pair and electrical power is transmitted over the twisted-pair while network data is transmitted wirelessly. Allowable Subject Matter Claims 1-20 are allowed, pending the filing of the terminal disclaimer as indicated above. The following is an examiner’s statement of reasons for allowance of claim 1: The prior art by Hazani WO 2018/178990 discloses a fault managed power system (FMPS) configured to provide at least 100 Watts of power, the FMPS comprising: a receiver [Fig. 4, remote unit 218] including a DC/DC converter [Fig. 4, DC/DC converter 421] and a receiver switch [Fig. 4, 416]; a source controller [Fig. 4, power distribution circuit 244] connected to the receiver by a pair of electrical conductors [Fig. 4, 246+ and 246-], the source controller including a source switch [Fig. 4, 408] configured to connect electrical power from a power source to the pair of electrical conductors. However, the prior art does not disclose that the receiver is configured to provide the DC/DC converter a series of current pulses that would not result in a person going into ventricular fibrillation from an electrical shock; the source controller is configured to determine whether a leakage current is present on either or both of the electrical conductors during a current-off interval of the series of current pulses, the leakage current being greater than a predetermined current threshold on either or both of the electrical conductors, and wherein the source controller is further configured to control the source switch to disconnect the power source from the electrical conductors in response to determining that the leakage current is present on either or both of the electrical conductors during the current-off interval of the series of current pulses. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record. The following is an examiner’s statement of reasons for allowance of claim 10: The prior art does not disclose a method of managing fault in a power system operable to provide at least 100 Watts of power, the method comprising: providing, at the receiver, a series of current pulses to a DC/DC converter that would not result in a person going into ventricular fibrillation from an electrical shock; determining, at the source controller, whether a leakage current is present on either or both of the electrical conductors during a current-off interval of the series of current pulses, the leakage current being greater than a preset current threshold on either or both of the electrical conductors; and disconnecting, at the source controller, the power source from the electrical conductors in response to determining that the leakage current is present on either or both of the electrical conductors during the current-off interval of the series of current pulses. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record. The following is an examiner’s statement of reasons for allowance of claim 19: The prior art does not disclose a fault managed power system (FMPS) that is configured to provide a series of current pulses having a current level that does not exceed a touch-safe level on at least one cable, wherein the FMPS is further configured to determine whether a leakage current is present on the at least one cable during a current-off interval of the series of current pulses, the leakage current being greater than a predetermined threshold current on the at least one cable. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DHARTI PATEL whose telephone number is (571)272-8659. The examiner can normally be reached M - F 9 AM - 5 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. DHARTI PATEL Primary Examiner Art Unit 2836 /DHARTI H PATEL/ Primary Examiner, Art Unit 2838
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Prosecution Timeline

Jan 13, 2025
Application Filed
Oct 16, 2026
Non-Final Rejection mailed — §DOUBLEPATENT (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
95%
With Interview (+7.7%)
2y 3m (~6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1272 resolved cases by this examiner. Grant probability derived from career allowance rate.

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