DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on March 10, 2026 has been entered and considered by the Examiner.
Claim Objections
Claims 24 and 26, and 41 is objected to because of the following informalities:
The claim recites limitation terms “plan view” in second line, fourth line, and second thru third lines of each claim respectively, but it’s not exactly clear whether the limitation terms are referring to same plan view recited in eleventh line of claim 1 and claim 39 respectively, or to a different plan view. Therefore, Examiner suggests the limitation terms should be amended, without adding new matter, in a manner that clarifies exactly what each of the limitation terms are referring to.
Claim 42 is objected to because of the following informalities:
The claim recites limitation term “a transistor” in second line of the claim, but it’s not exactly clear whether the limitation terms is referring to transistor recited in third thru fourth line\s of claim 40, or to a transistor. Therefore, Examiner suggests the limitation term should be amended, without adding new matter, in a manner that clarifies exactly what the limitation term is referring to.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 21, and 29-30 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, and 4-5, respectively of U.S. Patent No. 11,700,752 in view of Lius et al., U.S. Patent Application Publication 2021/0020810 A1 (hereinafter Lius). Although the claims at issue are not identical, they are not patentably distinct from each other because the scope of the independent claims, mentioned above, are substantially the same.
The following is an example for comparing claim 21 of this application and respective claim 1 of U.S. Patent No. 11,700,752:
Instant Application
U.S. Patent No.
11,700,752
Claim 21
Claim 1
A display device, comprising: a substrate; an active layer on a first surface of the substrate; a first insulating film located on the active layer; a first gate layer located on the first insulating film; a second insulating film located on the first gate layer; a second gate layer located on the second insulating film; a third insulating film located on the second gate layer; and
A display device comprising: a substrate; a first light blocking layer including a first hole and located on the substrate; a buffer film on the first light blocking layer; an active layer on the buffer film; a first insulating film on the active layer; a first gate layer on the first insulating film; a second insulating film on the first gate layer; a second gate layer on the second insulating film; a third insulating film on the second gate layer;
a first metal layer located on the third insulating film, and wherein a first hole comprises a first side extending in a first direction and a second side extending in a second direction crossing the first direction in plan view, and wherein the first side of the first hole comprises the first gate layer, and wherein the second side of the first hole comprises the active layer.
a data metal layer on the third insulating film; a first organic layer on the data metal layer; a second light blocking layer including a second hole and located on the first organic layer; a second organic layer on the second light blocking layer; and a light emitting element on the second organic layer, wherein a third hole is defined by the active layer, the first gate layer, the second gate layer, and the data metal layer.
Independent claim 21 of the instant application teaches “A display device, comprising: a substrate; an active layer on a first surface of the substrate; a first insulating film located on the active layer; a first gate layer located on the first insulating film; a second insulating film located on the first gate layer; a second gate layer located on the second insulating film; a third insulating film located on the second gate layer; and a first metal layer located on the third insulating film, and wherein a first hole comprises a first side extending in a first direction and a second side extending in a second direction crossing the first direction in plan view, and wherein the first side of the first hole comprises the first gate layer, and wherein the second side of the first hole comprises the active layer.” The U.S. Patent 11,700,752 does not expressly teach limitation(s): wherein a first hole comprises a first side extending in a first direction and a second side extending in a second direction crossing the first direction in plan view, and wherein the first side of the first hole comprises the first gate layer, and wherein the second side of the first hole comprises the active layer. However, Lius teaches wherein a first hole comprises a first side extending in a first direction and a second side extending in a second direction crossing the first direction in plan view, and wherein the first side of the first hole comprises the first gate layer, and wherein the second side of the first hole comprises the active layer (FIGS. 1 and 3, paragraph[0024] of Lius teaches the circuit layer 104 is disposed on the substrate 102, and may include various kinds of conductive lines, circuits and/or electronic elements such as switch element 110 and driving element 112; the switch element 110 and the driving element 112 may for example include a thin film transistor, but the present disclosure is not limited thereto; the switch element 110 may include a gate electrode 110G, a source electrode 110S, a drain electrode 110D, a semiconductor layer 110C and a first gate insulating layer GI; the first gate insulating layer GI is located between the gate electrode 110G and the semiconductor layer 110C; the gate electrode 110G of the switch element 110 may be electrically connected to the scan line (not shown in FIG. 1), and the source electrode 110S may be electrically connected to the data line DL; the driving element 112 may include a gate electrode 112G, a source electrode 112S, a drain electrode 112D, a semiconductor layer 112C and the first gate insulating layer GI; the first gate insulating layer GI is located between the gate electrode 112G and the semiconductor layer 112C; in an embodiment, the gate electrode 112G of the driving element 112 may be electrically connected to the drain electrode 110D of the switch element 110, the drain electrode 112D of the driving element 112 may be electrically connected to the second electrode 108c of the light emitting diode 108, and the source electrode 112S of the driving element 112 may be electrically connected to the working voltage source (VDD) or the common voltage source, but not limited thereto; besides, although the switch element 110 and the driving element 112 shown in FIG. 1 is a top gate thin film transistor, the present disclosure is not limited thereto; the switch element 110 and the driving element 112 may also include bottom gate thin film transistor or multi-gate thin film transistor (such as dual gate/double gate thin film transistor), and the switch element 110 and the driving element 112 may include the same type or different types of the thin film transistor; in an embodiment, the materials of the semiconductor layer 110C of the switch element 110 and the semiconductor layer 112C of the driving element 112 may respectively include amorphous semiconductor, poly-crystalline semiconductor, metal oxide (such as indium gallium zinc oxide (IGZO)), or the combinations thereof, but not limited thereto; the materials of the semiconductor layer 110C and the semiconductor layer 112C may be the same or different; and for example, the material of one of the semiconductor layer 110C and the semiconductor layer 112C may include poly-crystalline silicon, and the material of another one of the semiconductor layer 110C and the semiconductor layer 112C may include indium gallium zinc oxide, but not limited thereto, and See also at least paragraphs[0021]-[0023], and [0025]-[0032] of Lius (i.e., Lius teaches the electronic device having a data line disposed on the intermediate dielectric layer, wherein an opening, which has a first side that extends in a first direction and a second side that extends in a second direction that crosses the first direction, includes the gate electrode disposed on the first side, and wherein the semiconductor layer is disposed on the second side)).
Furthermore, U.S. Patent 11,700,752 and Lius are considered to be analogous art because they are from the same field of endeavor with respect to a display device, and involve the same problem forming the display device with a suitable optical sensor. Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to modify the apparatus of U.S. Patent 11,700,752 based on Lius wherein a first hole comprises a first side extending in a first direction and a second side extending in a second direction crossing the first direction in plan view, and wherein the first side of the first hole comprises the first gate layer, and wherein the second side of the first hole comprises the active layer. One reason for the modification as taught by Lius is to for an electronic device having a suitable optical sensor (paragraph[0001] of Lius). In addition, in regard to U.S. Patent 11,700,752, it would have been obvious to one of ordinary skill in the art to remove the further limitations “a first light blocking layer including a first hole and located on the substrate; a buffer film on the first light blocking layer; the buffer film; a first organic layer on the data metal layer; a second light blocking layer including a second hole and located on the first organic layer; a second organic layer on the second light blocking layer; and a light emitting element on the second organic layer, wherein a third hole is defined by the active layer, the first gate layer, the second gate layer, and the data metal layer”, since at least omitting the further limitations do not prevent the apparatus from functioning properly, and the claim is in “comprising” format indicating other elements could even be added. Moreover, dependent claims 29-30 of the instant application are rejected at least based on same above reasoning and given that their limitations are similar to claims 4-5 of U.S. Patent 11,700,752.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 21 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lius et al., U.S. Patent Application Publication 2021/0020810 A1 (hereinafter Lius).
Regarding claim 21, Lius teaches a display device, comprising: (200 FIGS. 1 and 3, paragraph[0032] of Lius teaches referring to FIG. 3, FIG. 3 schematically illustrates a cross-sectional view of an electronic device according to the second embodiment of the present disclosure; in order to simplify the figure, the functional layer and the protection layer which are selectively disposed are omitted in FIG. 3; the main difference between the electronic device 200 of the present embodiment and the electronic device of the first embodiment shown in FIG. 1 is that the second electrode 208c of the light emitting diode 208 of the electronic device 200 in the present embodiment may include an opening 208d; as shown in FIG. 3, the light emitting diode 208 may include a first electrode 208a, a light emitting layer 208b and a second electrode 208c, wherein an opening 208d may be included in the second electrode 208c, and the light emitting layer 208b may be filled into the opening 208d; the first electrode 208a and the second electrode 208c of the light emitting diode 208 may for example include metal oxide or metal material; for example, the first electrode 208a may include metal oxide material (such as indium tin oxide (ITO)), and the second electrode 208c may include conductive metal material, but not limited thereto; similarly, although only one light emitting diode 208 is shown in FIG. 3, the present disclosure is not limited thereto; the electronic device 200 may for example include two or more light emitting diodes; similar to the first embodiment, the optical sensor 206 of the present embodiment has a first region R1 not overlapping the light emitting diode 208 and a second region R2 overlapping the light emitting diode 208; the first region R1 of the optical sensor 206 may for example receive the light L1 to generate the first electrical signal for fingerprint authentication; the light L1 may be emitted from the light emitting diode 208, and may be reflected by the object FG to the optical sensor 206; the second region R2 of the optical sensor 206 may for example receive the light L2 emitted from the light emitting diode 208, and may for example generate the second electrical signal for luminance calibration of the light emitting diode 208, but the present disclosure is not limited to the above-mentioned contents; according to the present embodiment, the light L2 may for example be emitted from the light emitting layer 208b and reach the second region R2 of the optical sensor 206 through the opening 208d, but not limited thereto; and other elements or layers of the electronic device 200 of the present embodiment may be the same as or similar to the elements or layers in the first embodiment, and will not be redundantly described here, and See also at least paragraphs[0021]-[0030] of Lius (i.e., Lius teaches an electronic device)) a substrate (102 FIGS. 1 and 3, paragraph[0021] of Lius teaches referring to FIG. 1, FIG. 1 schematically illustrates a cross-sectional view of an electronic device according to the first embodiment of the present disclosure; the electronic device 100 may include a display device, antenna, sensing device or tiled device, but not limited thereto; the electronic device may be a foldable electronic device or a flexible electronic device; the electronic device 100 may for example be served as a common display, a tiled display, a vehicle display, a display panel, a touch panel, a light source module, a television, a smart phone, a tablet, a laptop, a lighting equipment or an electronic device applied to the above-mentioned products, but not limited to the above-mentioned examples; as shown in FIG. 1, the electronic device 100 may include a substrate 102, a circuit layer 104, an optical sensor 106 and a light emitting diode 108; and the substrate 102 may be a rigid substrate (such as glass substrate, quartz substrate, ceramic substrate or sapphire substrate, but not limited thereto), a flexible substrate (such as polyimide substrate, polycarbonate substrate, polyethylene terephthalate substrate or the like), other suitable substrate or the combinations of the above-mentioned substrates, but not limited thereto, and See also at least paragraphs[0022]-[0032] of Lius (i.e., Lius teaches the electronic device having a substrate)); an active layer on a first surface of the substrate; a first insulating film located on the active layer; a first gate layer located on the first insulating film (110C, GI, 110G FIGS. 1 and 3, paragraph[0024] of Lius teaches the circuit layer 104 is disposed on the substrate 102, and may include various kinds of conductive lines, circuits and/or electronic elements such as switch element 110 and driving element 112; the switch element 110 and the driving element 112 may for example include a thin film transistor, but the present disclosure is not limited thereto; the switch element 110 may include a gate electrode 110G, a source electrode 110S, a drain electrode 110D, a semiconductor layer 110C and a first gate insulating layer GI; the first gate insulating layer GI is located between the gate electrode 110G and the semiconductor layer 110C; the gate electrode 110G of the switch element 110 may be electrically connected to the scan line (not shown in FIG. 1), and the source electrode 110S may be electrically connected to the data line DL; the driving element 112 may include a gate electrode 112G, a source electrode 112S, a drain electrode 112D, a semiconductor layer 112C and the first gate insulating layer GI; the first gate insulating layer GI is located between the gate electrode 112G and the semiconductor layer 112C; in an embodiment, the gate electrode 112G of the driving element 112 may be electrically connected to the drain electrode 110D of the switch element 110, the drain electrode 112D of the driving element 112 may be electrically connected to the second electrode 108c of the light emitting diode 108, and the source electrode 112S of the driving element 112 may be electrically connected to the working voltage source (VDD) or the common voltage source, but not limited thereto; besides, although the switch element 110 and the driving element 112 shown in FIG. 1 is a top gate thin film transistor, the present disclosure is not limited thereto; the switch element 110 and the driving element 112 may also include bottom gate thin film transistor or multi-gate thin film transistor (such as dual gate/double gate thin film transistor), and the switch element 110 and the driving element 112 may include the same type or different types of the thin film transistor; in an embodiment, the materials of the semiconductor layer 110C of the switch element 110 and the semiconductor layer 112C of the driving element 112 may respectively include amorphous semiconductor, poly-crystalline semiconductor, metal oxide (such as indium gallium zinc oxide (IGZO)), or the combinations thereof, but not limited thereto; the materials of the semiconductor layer 110C and the semiconductor layer 112C may be the same or different; and for example, the material of one of the semiconductor layer 110C and the semiconductor layer 112C may include poly-crystalline silicon, and the material of another one of the semiconductor layer 110C and the semiconductor layer 112C may include indium gallium zinc oxide, but not limited thereto, and See also at least paragraphs[0021]-[0023], and [0025]-[0032] of Lius (i.e., Lius teaches the electronic device having a semiconductor layer disposed on the substrate, a first gate insulating layer disposed on the semiconductor layer, and a gate electrode disposed on the first gate insulating layer)); a second insulating film located on the first gate layer; a second gate layer located on the second insulating film (112G FIGS. 1 and 3, paragraph[0024] of Lius teaches the circuit layer 104 is disposed on the substrate 102, and may include various kinds of conductive lines, circuits and/or electronic elements such as switch element 110 and driving element 112; the switch element 110 and the driving element 112 may for example include a thin film transistor, but the present disclosure is not limited thereto; the switch element 110 may include a gate electrode 110G, a source electrode 110S, a drain electrode 110D, a semiconductor layer 110C and a first gate insulating layer GI; the first gate insulating layer GI is located between the gate electrode 110G and the semiconductor layer 110C; the gate electrode 110G of the switch element 110 may be electrically connected to the scan line (not shown in FIG. 1), and the source electrode 110S may be electrically connected to the data line DL; the driving element 112 may include a gate electrode 112G, a source electrode 112S, a drain electrode 112D, a semiconductor layer 112C and the first gate insulating layer GI; the first gate insulating layer GI is located between the gate electrode 112G and the semiconductor layer 112C; in an embodiment, the gate electrode 112G of the driving element 112 may be electrically connected to the drain electrode 110D of the switch element 110, the drain electrode 112D of the driving element 112 may be electrically connected to the second electrode 108c of the light emitting diode 108, and the source electrode 112S of the driving element 112 may be electrically connected to the working voltage source (VDD) or the common voltage source, but not limited thereto; besides, although the switch element 110 and the driving element 112 shown in FIG. 1 is a top gate thin film transistor, the present disclosure is not limited thereto; the switch element 110 and the driving element 112 may also include bottom gate thin film transistor or multi-gate thin film transistor (such as dual gate/double gate thin film transistor), and the switch element 110 and the driving element 112 may include the same type or different types of the thin film transistor; in an embodiment, the materials of the semiconductor layer 110C of the switch element 110 and the semiconductor layer 112C of the driving element 112 may respectively include amorphous semiconductor, poly-crystalline semiconductor, metal oxide (such as indium gallium zinc oxide (IGZO)), or the combinations thereof, but not limited thereto; the materials of the semiconductor layer 110C and the semiconductor layer 112C may be the same or different; and for example, the material of one of the semiconductor layer 110C and the semiconductor layer 112C may include poly-crystalline silicon, and the material of another one of the semiconductor layer 110C and the semiconductor layer 112C may include indium gallium zinc oxide, but not limited thereto, and See also at least paragraphs[0021]-[0023], and [0025]-[0032] of Lius (i.e., Lius teaches the electronic device having the gate insulating layer disposed on the gate electrode, and other gate electrode disposed on a corresponding gate insulating layer)); a third insulating film located on the second gate layer (ILD FIGS. 1 and 3, paragraph[0030] of Lius teaches in an embodiment, a planarization layer PLN may be disposed on the optical sensor 106, and may provide a flat surface PLNS in order to dispose the second electrode 108c and the light emitting layer 108b which are subsequently formed, but not limited thereto; a functional layer FL and a protection layer CG may be selectively included in the electronic device 100 of the present disclosure; the functional layer FL may be served to provide the optical function or the touch function required by the electronic device 100, and the protection layer CG may for example be configured to protect the functional layer FL and other layers and/or elements below the functional layer FL, but not limited thereto; the electronic device 100 may further include an insulating layer 120 disposed on the pixel defining layer 114 and the light emitting diode 108; in some embodiments, the insulating layer 120 may be a single layer structure or a multi-layer structure; for example, the insulating layer 120 may include a first insulating layer 120a, a second insulating layer 120b and a third insulating layer 120c, the first insulating layer 120a and the third insulating layer 120c may for example include inorganic insulating materials, and the second insulating layer 120b may for example include organic insulating materials, but not limited thereto; in an embodiment, the insulating layer 120 may also provide planarization effect; and except for the above-mentioned elements or layers, the electronic device 100 of the present embodiment may for example include a buffer layer BF disposed on the light shielding layer LS, an intermediate dielectric layer ILD disposed on the first gate insulating layer GI, an insulating layer BP1 disposed on the intermediate dielectric layer ILD and an insulating layer BP2 disposed on the second gate insulating layer GI2, but not limited thereto, and See also at least paragraphs[0021]-[0029], and [0031]-[0032] of Lius (i.e., Lius teaches the electronic device having an intermediate dielectric layer disposed on the other gate electrode)); and a first metal layer located on the third insulating film, and wherein a first hole comprises a first side extending in a first direction and a second side extending in a second direction crossing the first direction in plan view, and wherein the first side of the first hole comprises the first gate layer, and wherein the second side of the first hole comprises the active layer (DL FIGS. 1 and 3, paragraph[0024] of Lius teaches the circuit layer 104 is disposed on the substrate 102, and may include various kinds of conductive lines, circuits and/or electronic elements such as switch element 110 and driving element 112; the switch element 110 and the driving element 112 may for example include a thin film transistor, but the present disclosure is not limited thereto; the switch element 110 may include a gate electrode 110G, a source electrode 110S, a drain electrode 110D, a semiconductor layer 110C and a first gate insulating layer GI; the first gate insulating layer GI is located between the gate electrode 110G and the semiconductor layer 110C; the gate electrode 110G of the switch element 110 may be electrically connected to the scan line (not shown in FIG. 1), and the source electrode 110S may be electrically connected to the data line DL; the driving element 112 may include a gate electrode 112G, a source electrode 112S, a drain electrode 112D, a semiconductor layer 112C and the first gate insulating layer GI; the first gate insulating layer GI is located between the gate electrode 112G and the semiconductor layer 112C; in an embodiment, the gate electrode 112G of the driving element 112 may be electrically connected to the drain electrode 110D of the switch element 110, the drain electrode 112D of the driving element 112 may be electrically connected to the second electrode 108c of the light emitting diode 108, and the source electrode 112S of the driving element 112 may be electrically connected to the working voltage source (VDD) or the common voltage source, but not limited thereto; besides, although the switch element 110 and the driving element 112 shown in FIG. 1 is a top gate thin film transistor, the present disclosure is not limited thereto; the switch element 110 and the driving element 112 may also include bottom gate thin film transistor or multi-gate thin film transistor (such as dual gate/double gate thin film transistor), and the switch element 110 and the driving element 112 may include the same type or different types of the thin film transistor; in an embodiment, the materials of the semiconductor layer 110C of the switch element 110 and the semiconductor layer 112C of the driving element 112 may respectively include amorphous semiconductor, poly-crystalline semiconductor, metal oxide (such as indium gallium zinc oxide (IGZO)), or the combinations thereof, but not limited thereto; the materials of the semiconductor layer 110C and the semiconductor layer 112C may be the same or different; and for example, the material of one of the semiconductor layer 110C and the semiconductor layer 112C may include poly-crystalline silicon, and the material of another one of the semiconductor layer 110C and the semiconductor layer 112C may include indium gallium zinc oxide, but not limited thereto, and See also at least paragraphs[0021]-[0023], and [0025]-[0032] of Lius (i.e., Lius teaches the electronic device having a data line disposed on the intermediate dielectric layer, wherein an opening, which has a first side that extends in a first direction and a second side that extends in a second direction that crosses the first direction, includes the gate electrode disposed on the first side, and wherein the semiconductor layer is disposed on the second side)).
Potentially Allowable Subject Matter
Claims 37 and 39 are allowable, because the prior art references of record do not teach the combination of all element limitations as presently claimed. For example, in regard to claim 37 the prior art of record at least does not expressly teach concept of wherein a first hole comprises a first side extending in a first direction and a second side extending in a second direction crossing the first direction in plan view, and wherein the first side of the first hole comprises one layer of the active layer, the first gate layer, the second gate layer and the data metal layer, and wherein the second side of the first hole comprises another layer of the active layer, the first gate layer, the second gate layer and the data metal layer. Still for example, in regard to claim 39 the prior art of record at least does not expressly teach concept of wherein a first hole comprises: a first side extending a first direction in plan view; a second side extending a second direction crossing the first direction in plan view; and a third side opposite to the second side and extending in the first direction, and wherein the first side of the first hole comprises the first gate layer, and wherein the second side of the first hole comprises the active layer, and wherein the third side of the first hole comprises the second gate layer. In addition, claims 38 and 40-42 would be allowable if rewritten to overcome applicable objection(s), if any, because for each of claims 38 and 40-42, at least in light of their dependency on their respective independent claims, the prior art references of record do not teach the combination of all element limitations as presently claimed. Claims 22-36 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to overcome applicable objection(s), if any, and if rewritten in independent form including all of the limitations of the base claim and any intervening claims, because for each of claims 22-36 the prior art references of record do not teach the combination of all element limitations as presently claimed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABDUL-SAMAD A ADEDIRAN whose telephone number is (571)272-3128. The examiner can normally be reached Monday through Thursday, 8:00 am to 5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amr Awad can be reached on 571-272-7764. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ABDUL-SAMAD A ADEDIRAN/Primary Examiner, Art Unit 2621
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