DETAILED ACTION
This Office Action, based on application 19/019,543 filed 14 January 2025, is entered responsive to applicant’s amendment and remarks filed 24 March 2026. Claims 1-18 are currently pending and have been fully considered below.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s remarks, filed 24 March 2026 in response to the Office Action mailed 16 January 2026, have been fully considered below.
Specification Objection
The Office withdraws the previously issued objection in view of applicant’s title amendment.
Claim Rejections under 35 U.S.C. § 112
The Office withdraws the previously issued indefiniteness rejection in view of applicant’s amendment and remarks.
Claim Rejections under 35 U.S.C. § 102/103
The applicant traverses the prior art rejection alleging cited prior art fails to disclose each feature of Claim 1. The applicant asserts KOMAKI’s teaching of the GPO1 signal is not analogous to the claimed ‘trigger signal’ since the signal KOMAKI teaches that “the signal at the GPO1 terminal of the system controller is output to the RST terminal of the XDR DRAMs instead of receiving from the RST terminal of the XDR DRAMs”. The Office maintains “The GPO1 signal provided by the system controller analogous to ‘the trigger signal’ as the signal resets DRAMs or suspends the DRAMs based on the terminal level” thus performing the function of maintaining a power supply to the memory array during a reset period. The Office further asserts the signal must be generated somehow and is thus received. The Office further cites ¶[0042] explicitly teaching the system controller setting the GPO1 terminal in response to a received signal (GP10 terminal); as such, the Office maintains the prior art reference anticipates at least the features of Claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5, 6, 9, 10, 13, and 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KOMAKI (US PGPub 2010/0138597).
KOMAKI discloses:
Claim 1: A memory storage apparatus, comprising:
a memory array, configured to store data (Fig 1, XRD DRAM 13); and
a controller circuit (Fig 1, STR Control Circuit 14, Memory Control Circuit 12, System Controller 11), coupled to the memory array and configured to receive a reset signal and a trigger signal, wherein the controller circuit performs a reset operation according to the reset signal, and the controller circuit maintains a power supply to the memory array according to the trigger signal during a reset period (Abstract – “When shutting down power of a system while suspending data stored in the extreme data rate DRAM, the system controller shuts down power of the memory controller while maintaining supply of power to the extreme data rate DRAM in response to the reset signal input from the memory controller through the level shifter.”. The signal provided from the memory controller to the system controller analogous to ‘the reset signal’ as the signal initiates a ‘Cold Boot’ mode {Fig 3} and a ‘Enter-To-Suspend’/’Warm Boot’ mode {Figs 4 and 5}. ¶[0076]; ¶[0031] - The GPO1 signal provided by the system controller analogous to ‘the trigger signal’ as the signal resets DRAMs or suspends the DRAMs based on the terminal level; ¶[0042] – “The system controller 11 sets the GPO1 terminal (RST) to the low level in response to the low level of the GP10 terminal”).
Claim 9: A method for operating a memory storage apparatus, wherein the memory storage apparatus comprises a memory array (Fig 1, XRD DRAM 13), the method for operating comprising:
receiving a reset signal (Fig 2, RST of Memory Controller 12) and a trigger signal (Fig 2, GP01);
performing a reset operation according to the reset signal; and
maintaining a power supply to the memory array according to the trigger signal during a reset period (Abstract – “When shutting down power of a system while suspending data stored in the extreme data rate DRAM, the system controller shuts down power of the memory controller while maintaining supply of power to the extreme data rate DRAM in response to the reset signal input from the memory controller through the level shifter.”. The signal provided from the memory controller to the system controller analogous to ‘the reset signal’ as the signal initiates a ‘Cold Boot’ mode {Fig 3} and a ‘Enter-To-Suspend’/’Warm Boot’ mode {Figs 4 and 5}. ¶[0076]; ¶[0031] - The GPO1 signal provided by the system controller analogous to ‘the trigger signal’ as the signal resets DRAMs or suspends the DRAMs based on the terminal level; ¶[0042] – “The system controller 11 sets the GPO1 terminal (RST) to the low level in response to the low level of the GP10 terminal”).
Claim 16: A memory storage apparatus, comprising:
a memory array (Fig 1, XRD DRAM 13), configured to store data; and
a controller circuit (Fig 2, RST of Memory Controller 12), coupled to the memory array and configured to receive a reset signal (Fig 2, GP01), wherein the reset signal is used as a trigger signal, and
wherein the controller circuit performs a reset operation according to the reset signal, and the controller circuit maintains a power supply to the memory array according to the trigger signal during a reset period (Abstract – “When shutting down power of a system while suspending data stored in the extreme data rate DRAM, the system controller shuts down power of the memory controller while maintaining supply of power to the extreme data rate DRAM in response to the reset signal input from the memory controller through the level shifter.”. The signal provided from the memory controller to the system controller analogous to ‘the reset signal’ as the signal initiates a ‘Cold Boot’ mode {Fig 3} and a ‘Enter-To-Suspend’/’Warm Boot’ mode {Figs 4 and 5}. ¶[0076]; ¶[0031] - The GPO1 signal provided by the system controller analogous to ‘the trigger signal’ as the signal resets DRAMs or suspends the DRAMs based on the terminal level).
Claims 2 and 10: The apparatus/method according to each respective parent claim, further comprising performing a self-refresh operation on the memory array after executing the reset operation (¶[0049] – “ the memory controller 12 firmware executes "Power-down Sequence" of the XDR DRAM 13. As a result, the XDR DRAM 13 is brought into a self-refresh mode with less power consumption”).
Claims 5 and 13: The apparatus/method according to each respective parent claim, wherein the trigger signal is a combination of an external signal input to a pin of the memory storage apparatus (Fig 2, GP01 drives RST input of each DRAMx).
Claims 6 and 14: The apparatus/method according to each respective parent claim, wherein the combination of the external signal comprises signal type or voltage level (Fig 2, GP01 drives RST input of each DRAMx).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 3, 8, and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOMAKI in further view of ISHIHARA (US PGPub 2005/0283572).
With respect to Claims 3 and 11, KOMAKI discloses the apparatus/method according to each respective parent claim.
KOMAKI may not explicitly disclose stopping the self-refresh operation according to a reference signal.
However, ISHIHARA discloses stopping the self-refresh operation according to a reference signal (¶[0047] – “the CPU 11 issues a self-refresh release command to the DRAM control circuit 15. At time T13, the DRAM control circuit 15 outputs a clock control signal CKEI at a low level, and outputs a chip select signal CSI, a row address select signal RASI, a column address select signal CASI, a write control signal WEI, and data output mask signals DQMI3 to DQMI0 at a high level, on the basis of the self-refresh release command. The self-refresh state of the SDRAM 40 is thereby released.”).
KOMAKI and ISHIHARA are analogous art because they are from the same field of endeavor of management and control of volatile memory. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of KOMAKI and ISHIHARA before him or her, to modify the controller of KOMAKI to include controlling start and release self-refresh mode signals as taught by ISHIHARA. A motivation for doing so would have been to enable the interruption and resuming of application programs (¶0048]) which may be performed for power-saving purposes. Therefore, it would have been obvious to combine KOMAKI and ISHIHARA to obtain the invention as specified in the instant claims.
With respect to Claim 8, KOMAKI discloses the memory storage apparatus according to claim 1.
KOMAKI further discloses a power supply circuit, coupled to the memory array and the controller circuit, and configured to provide a power supply to the memory array during the reset period (¶[0049] – “ the memory controller 12 firmware executes "Power-down Sequence" of the XDR DRAM 13. As a result, the XDR DRAM 13 is brought into a self-refresh mode with less power consumption”).
KOMAKI may not explicitly disclose wherein the power supply circuit determines whether to maintain the power supply to the memory array during the reset period according to a command of the controller circuit.
However, ISHIHARA discloses wherein the power supply circuit determines whether to maintain the power supply to the memory array during the reset period according to a command of the controller circuit (¶[0047] – “the CPU 11 issues a self-refresh release command to the DRAM control circuit 15. At time T13, the DRAM control circuit 15 outputs a clock control signal CKEI at a low level, and outputs a chip select signal CSI, a row address select signal RASI, a column address select signal CASI, a write control signal WEI, and data output mask signals DQMI3 to DQMI0 at a high level, on the basis of the self-refresh release command. The self-refresh state of the SDRAM 40 is thereby released.”).
Claim(s) 4, 7, 12, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOMAKI in further view of PALMER (US PGPub 2020/0210073).
With respect to Claims 4 and 12, KOMAKI discloses the apparatus/method according to each respective parent claim.
KOMAKI may not explicitly disclose wherein the self-refresh operation is performed on the memory array after the reset period is greater than a preset time length.
However, PALMER discloses wherein the self-refresh operation is performed on the memory array after the reset period is greater than a preset time length (¶[0023] – “ the control logic 150 can also include one or more circuits to initialize the timer 155 with an indicated value, such as a number of timer ticks or units of time that must pass before the reset logic 145 executes a reset”).
KOMAKI and PALMER are analogous art because they are from the same field of endeavor of management and control of volatile memory. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of KOMAKI and PALMER before him or her, to modify the controller of KOMAKI to include a timer circuit controlling a reset signal as taught by PALMER. A motivation for doing so would have been to cause the storage device to execute a reset even when a storage controller is deadlocked or otherwise malfunctioning (¶[0029]). Therefore, it would have been obvious to combine KOMAKI and PALMER to obtain the invention as specified in the instant claims.
With respect to Claims 7, 15, 17, and 18, KOMAKI discloses the apparatus/methods according to each respective parent claim.
KOMAKI further discloses wherein the trigger signal comprises a second reset signal (Abstract – “When shutting down power of a system while suspending data stored in the extreme data rate DRAM, the system controller shuts down power of the memory controller while maintaining supply of power to the extreme data rate DRAM in response to the reset signal input from the memory controller through the level shifter.”. The signal provided from the memory controller to the system controller analogous to ‘the reset signal’ as the signal initiates a ‘Cold Boot’ mode {Fig 3} and a ‘Enter-To-Suspend’/’Warm Boot’ mode {Figs 4 and 5}. ¶[0076]; ¶[0031] - The GPO1 signal provided by the system controller analogous to ‘the trigger signal’ as the signal resets DRAMs or suspends the DRAMs based on the terminal level).
KOMAKI may not explicitly disclose a time length of the second reset signal is used to determine whether to trigger an operation of maintaining the power supply to the memory array during the reset period.
However, PALMER discloses a time length of the second reset signal is used to determine whether to trigger an operation of maintaining the power supply to the memory array during the reset period (¶[0023] – “ the control logic 150 can also include one or more circuits to initialize the timer 155 with an indicated value, such as a number of timer ticks or units of time that must pass before the reset logic 145 executes a reset”).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC T LOONAN whose telephone number is (571)272-6994. The examiner can normally be reached M-F 8am-5pm.
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/ERIC T LOONAN/Examiner, Art Unit 2137
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