DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 and 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2022/0051606) in view of Wu (US 2024/0355266) and Bae et al. (US 2021/0295782).
Regarding claim 1, Kim discloses a display device comprising: a display panel including data lines and pixel blocks connected to the data lines (figs. 1-2, ¶ 43-46, data lines D with pixels PX, see also ¶ 51);
data drivers connected to the pixel blocks, respectively, each configured to supply data signals to respective data lines (figs. 1-2, ¶ 43-46, data driver 300, see also ¶ 65-66, figs. 9-10, ¶ 148-163, e.g., buffers 380);
and a timing controller configured to control the data drivers (fig. 1, controller 400, see ¶ 52-66),
wherein each of the data drivers is configured to adjust slew rates of the data signals by decoding the respective data signals, generating a respective bias signal based on a position of the respective pixel block relative to the display panel, and applying the generated bias signal to the decoded data signals (figs. 2-5, ¶ 72-85, see also figs. 9-10, ¶ 148-163, output delay time and slew rate controlled based on position and load; see also ¶ 114-116, DAC 360 converts latched image data; see also ¶ 65-66, data driver and controller may be included in one source IC, data driver may be configured with a plurality of data drivers for driving the partial areas of the pixel unit),
and wherein the timing controller is configured to calculate a grayscale value of the image, based on an input grayscale value of the input image data, an input luminance value of the input image data, and a load value of each of the pixel blocks (fig. 1, figs. 6-9, ¶ 52-66, controller generates image data based on input image data, see also ¶ 98-117, data signals adjusted based on load and gamma).
Kim fails to explicitly disclose adjusting slew rates of the data signals based on a maximum grayscale value of input image data to be displayed through the pixel blocks, wherein the timing controller is configured to calculate the maximum grayscale value of the image.
Wu teaches wherein the timing controller is configured to calculate the maximum grayscale value of the image (figs. 1-2, fig. 6, ¶ 16-23, maximum gray level of each region determined and mapped to luminance to determine voltage level setting of each region).
Kim and Wu are both directed to display driving for LED displays. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Kim with the device of Wu since such a modification allows driving LED units on a regional basis (Wu, ¶ 18) and reduces power consumption (Wu, ¶ 30).
Bae teaches adjusting slew rates of the data signals based on a maximum grayscale value of input image data to be displayed through the pixel blocks (figs. 3-8, see ¶ 78-88, source bias current is set based on luminance of the image).
Kim in view of Wu and Bae are both directed to slew rate control for an LED display. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Kim in view of Wu with the device of Bae since such a modification reduces power consumption (Bae, ¶ 10) and controls a slew rate in real time (Bae, ¶ 11).
Regarding claim 2, Kim discloses wherein each of the data drivers includes: an output buffer configured to output any one of the data signals to any one of the data lines (figs. 1-2, ¶ 43-46, data driver 300, see also ¶ 65-66, figs. 9-10, ¶ 148-163, e.g., buffers 380);
a current supplier configured to supply a bias current to the output buffer (figs. 9-10, ¶ 148-163, slew rate controller adjusts bias current);
a current controller configured to adjust an intensity of the bias current, based on the maximum grayscale value of the image (figs. 9-10, ¶ 148-163, slew rate controller adjusts bias current);
and a data output controller configured to adjust an output timing of any one of the data signals, based on the maximum grayscale value of the image (figs. 2-5, ¶ 72-85, see also figs. 9-10, ¶ 148-163, output delay time and slew rate controlled).
Regarding claim 3, Kim discloses wherein the current controller increases the intensity of the bias current as the maximum grayscale value becomes larger, and wherein the data output controller delays the output timing of any one of the data signals as the maximum grayscale value becomes larger (figs. 2-5, ¶ 72-85, see also figs. 9-10, ¶ 148-163, output delay time and slew rate controlled).
Regarding claim 4, Wu further teaches wherein the pixel blocks include: a first pixel block disposed adjacent to a corner of the display panel; and a second pixel block disposed adjacent to the first pixel block, and wherein the maximum grayscale value of each of the first pixel block and the second pixel block has any one of a first grayscale value, a second grayscale value, and a third grayscale value (figs. 1-2, fig. 6, ¶ 16-23, maximum gray level of each region determined and mapped to luminance to determine voltage level setting of each region).
Regarding claim 5, Kim discloses wherein the current controller is configured to supply any one of a first bias current, a second bias current, and a third bias current to each of a first output buffer corresponding to the first pixel block and a second output buffer corresponding to the second pixel block (figs. 9-10, ¶ 148-163, slew rate controller adjusts bias current),
and wherein the data output controller outputs the data signals supplied to the first pixel block and the second pixel block at any one of a first time point, a second time point, and a third time point (figs. 2-5, ¶ 72-85, see also figs. 9-10, ¶ 148-163, output delay time controlled based on position and load).
Regarding claim 6, Kim discloses wherein, when the maximum grayscale value of the first pixel block is the first grayscale value, the current controller is configured to supply the first bias current to the first output buffer (figs. 9-10, ¶ 148-163, slew rate controller adjusts bias current),
and the data output controller outputs the data signal supplied to the first pixel block at the first time point (figs. 2-5, ¶ 72-85, see also figs. 9-10, ¶ 148-163, output delay time controlled based on position and load).
Regarding claim 11, Kim discloses wherein the pixel blocks further include a third pixel block disposed more adjacent to the first pixel block than the second pixel block, and wherein the data drivers independently control the first to third pixel blocks (figs. 1-2, ¶ 43-46, data driver 300, see also ¶ 65-66, figs. 9-10, ¶ 148-163, e.g., buffers 380).
Regarding claim 12, Kim discloses wherein the current controller is configured to supply the first bias current to a third output buffer corresponding to the third pixel block (figs. 9-10, ¶ 148-163, slew rate controller adjusts bias current),
and wherein the data output controller outputs the data signal supplied to the third pixel block at the first time point (figs. 2-5, ¶ 72-85, see also figs. 9-10, ¶ 148-163, output delay time controlled based on position and load).
Regarding claim 13, Bae further teaches wherein the timing controller calculates the maximum grayscale value to be in inverse proportion to the input grayscale value, the input luminance value, and the load value (fig. 7, see ¶ 98-101, as grayscale value increases, source voltage decreases, e.g., source voltage has max value at gray level 0),
wherein each data driver simultaneously controls an intensity of the bias signal and an output timing of the data signal (figs. 2-5, ¶ 72-85, see also figs. 9-10, ¶ 148-163, output delay time and slew rate controlled based on position and load; see also ¶ 65-66, data driver and controller may be included in one source IC, data driver may be configured with a plurality of data drivers for driving the partial areas of the pixel unit).
Regarding claim 14, this claim is rejected under the same rationale as claim 1.
Regarding claim 15, this claim is rejected under the same rationale as claim 1.
Regarding claim 16, this claim is rejected under the same rationale as claim 1.
Regarding claim 17, this claim is rejected under the same rationale as claim 13.
Regarding claim 18, Wu further teaches wherein the timing controller includes: a memory configured to store a lookup table including bias current data supplied to the data lines and output timing data of the data signals (figs. 1-2, fig. 4, ¶ 16-23, maximum gray level of each region determined and mapped to luminance to determine voltage level setting of each region; mapping table disclosed);
Kim discloses a data slew rate determiner configured to determine a data slew rate option corresponding to the maximum grayscale value, based on the lookup table (figs. 9-10, ¶ 148-163, slew rate controller adjusts bias current).
Regarding claim 19, this claim is rejected under the same rationale as claim 2.
Regarding claim 20, this claim is rejected under the same rationale as claim 1.
Claims 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Wu and Bae as applied to claim 5 above, and further in view of Shi et al. (US 2023/0089942).
Regarding claim 7, Kim in view of Wu and Bae fail to explicitly disclose wherein, when the maximum grayscale value of the first pixel block is the second grayscale value greater than the first grayscale value, the current controller is configured to supply the second bias current greater than the first bias current to the first output buffer, and the data output controller outputs the data signal supplied to the first pixel block at the second time point later than the first time point.
Shi teaches wherein, when the maximum grayscale value of the first pixel block is the second grayscale value greater than the first grayscale value, the current controller is configured to supply the second bias current greater than the first bias current to the first output buffer, and the data output controller outputs the data signal supplied to the first pixel block at the second time point later than the first time point (abstract, figs. 6-12, see ¶ 5-8, 2D digital and local analog compensation zone map for voltage error based on position disclosed, higher luminance may correlate to a larger voltage error; voltage error relationship relates a modeled or empirically determined voltage error corresponding to APL, global brightness, and load/current; see also ¶ 40-42, ¶ 65-71, analog and digital compensation determine a compensation required to provide the display pixels with the correct voltage, compensation may or may not be linear across the display).
Kim in view of Wu and Bae and Shi are both directed to positional voltage compensation for LED displays. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Kim in view of Wu and Bae with the modeled or empirically determined 2D compensation map of Shi since such a modification compensates for linear and non-linear voltage error across the display (Shi, ¶ 7) and determines a compensation required to provide the display pixels with the correct voltage (Shi, ¶ 65).
Regarding claim 8, this claim is rejected under the same rationale as claim 7.
Regarding claim 9, this claim is rejected under the same rationale as claim 7.
Regarding claim 10, this claim is rejected under the same rationale as claim 7.
Response to Arguments
Applicant's arguments filed 2/27/26 have been fully considered but they are not persuasive. Regarding claims 1, 14, and 20, Applicant argues “KIM does not disclose any data drivers that control the slew rate” and “KIM’s timing controller is not scalable to provide different bias signals to each data driver” (Remarks, pp. 16-17).
Examiner disagrees. As cited in the above rejection, ¶ 65-66 of Kim explicitly disclose that the data driver and controller may be included in one source IC, and further that the data driver may be configured with a plurality of data drivers for driving the partial areas of the pixel unit. Thus Kim discloses that each data driver can adjust slew rates based on a generated bias signal as show in, e.g., fig. 9A of Kim. Applicant’s remaining arguments amount to piecemeal analysis and/or bodily incorporation of the references, and are therefore not persuasive.
The rejection of the claims is maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KEITH L CRAWLEY/Primary Examiner, Art Unit 2626
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