DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
Paragraph [0057], line 7 of page 12, should read as, “. . . the programming level of a plurality of programming levels. . . .”
Appropriate correction is required.
Claim Objections
Claims 3 and 13 objected to because of the following informalities:
Claim 3, lines 1-2, should read as, “The method of claim 1, wherein verifying whether the memory cells are programmed to a programming level of [[a]]the plurality of programming levels . . .”
Claim 13, lines 1-2, should read as, “The memory device of claim 11, wherein verifying whether the memory cells are programmed to a programming level of [[a]]the plurality of programming levels . . .”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 2 and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 2 and 12 recite, “a programming level of the memory cells for verifying whether the memory cells are programmed to the programming level is equal to a programming level of the memory cells during the read operation of the memory cells.” (emphasis added) The distinction, if any, between “a programming level of the memory cells for verifying” and “a programming level of the memory cells during the read operation of the memory cells” is unclear. That is, reciting “a programming level” in two different contexts without a unique identifier associated with or signaling the difference between each instance identified by separate limitations creates ambiguity between each instance of “a programming level.” Moreover, “programming levels” are not typically applied to word lines or memory cells during verify and read operations, further mystifying what the applicant intended to express in claims 2 and 12.
Presumably, the applicant intended claims 2 and 12 express “a verify voltage level of the memory cells for verifying whether the memory cells are programmed” is equal to “a read voltage level of the memory cells during the read operation of the memory cells.” However, the specification contains statements using the same terminology found in the claims (paras. [0006], [0016], and [0076]); therefore, the intended limitation is uncertain.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5, 11-15, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lu et al. (US 20240071530 A1; hereinafter "Lu").
Regarding claim 1, Lu discloses a method of operating a memory device (FIG. 1B: memory device 130), comprising: programming memory cells coupled to a first word line (para. [0023]: “. . . sequentially applying programming voltage pulses to a selected or target wordline (WLn).”); verifying whether the memory cells are programmed to a programming level of a plurality of programming levels (para. [0023]: “After each programming pulse, or after a number of programming pulses, a program verify operation can be performed to determine if the threshold voltage of the one or more memory cells has increased to a desired programming level.”), comprising a verify voltage to the first word line (para. [0030]: “In a program verify operation, a read voltage is applied to the target wordline connected to the control gate of the selected memory cell.”); and applying a first pass voltage to one or more second word lines adjacent to the first word line (para. [0030]: “In addition, a program verify pass through voltage is applied to the wordlines connected to the control gates of the unselected memory cells.”; para. [0031]: “the program verify (PV) pass through voltage is applied to neighboring wordlines (e.g., WLn−1 and WLn+1) while the read voltage is applied to read the target wordline (WLn) to verify the programming state (e.g., whether the target wordline has reached the target programming level)”), wherein a value of the first pass voltage is lower than a value of a second pass voltage applied to the one or more second word lines when performing a read operation on the memory cells coupled to the first word line (para. [0033]: “During the read sub-operation, a program verify (PV) pass through voltage (herein referred to as the “PV pass voltage” or “Vpass(pv)”) is applied to the immediately adjacent or neighboring wordlines (WLn−1 and WLn+1) that has a voltage that is less than a pass through voltage applied to the neighboring wordlines in a read operation (Vpass(read))”).
Regarding claim 2, Lu discloses a programming level of the memory cells for verifying whether the memory cells are programmed to the programming level is equal to a programming level of the memory cells during the read operation of the memory cells (para. [0033]: “The program verify operation includes application of a program verify voltage level (Vpv) corresponding to a target programming level to the target wordline (WLn) to verify if programming at the target level is complete.”).
Regarding claim 3, Lu teaches verifying whether the memory cells are programmed to a programming level of a plurality of programming levels further comprises: applying a third pass voltage to remaining word lines of the memory device other than the first word line and the one or more second word lines, wherein a value of the third pass voltage is equal to a value of a fourth pass voltage applied to the remaining word lines when performing the read operation on the memory cells (para. [0026]: “It is noted that only one cell per bitline can be read at a time. Since the cells of a bitline are connected in series, all transistors for cells of the bitline that are not being read (“unread cells”) need to be kept on during the read operation in order for the read output of the read cell to pass through to the sense amplifier. To achieve this, a pass through voltage (Vpass) can be applied to the wordlines of the unread cells to keep the unread cells on.”—Official Notice: applying a pass voltage to each unselected word line to access data in a selected cell in either a verify or read operation is necessary in a string of NAND memory, and applying the same pass voltage to unselected word lines in a verify and read operation is common in the art (e.g. see Choi et al. (US 20250285689 A1) at para. [0052]; and Lee (US 20250087271 A1) at para. [0025])).
Regarding claim 4, Lu discloses the first pass voltage is determined based on the verify voltage of the first word line, a value of the first pass voltage decreases when a value of the verify voltage increases (FIG. 4A, para. [0035]: “”In this embodiment, the PV offset can incrementally increase as the corresponding target programming level of the target wordline increases. Accordingly, the PV offset increases as a function of the programming level (e.g., PV offset 1 for L1<PV offset 2 for L2<PV offset 3 for L3, and so on). For example, the Vpass(pv) applied to WLn−1 and WLn+1 can be determined based on a first PV offset (e.g., PV offset 1) when the target wordline (WLn) is programmed to a first programming level (L1).”—Verify voltage is inherently proportional to the programming level (threshold voltage); therefore, Lu teaches the pass voltage decreases as the programming level and the corresponding required verify voltage to verify the programming level increase).
Regarding claim 5, Lu teaches the plurality of programming levels are sorted into a plurality of groups arranged in an ascending order, wherein a same value of the first pass voltage is applied when verifying programming levels in a same group, a lower value of the first pass voltage is applied when verifying programming levels in a group with higher order (para. [0035]: “Accordingly, the PV offset increases as a function of the programming level (e.g., PV offset 1 for L1<PV offset 2 for L2<PV offset 3 for L3, and so on). For example, the Vpass(pv) applied to WLn−1 and WLn+1 can be determined based on a first PV offset (e.g., PV offset 1) when the target wordline (WLn) is programmed to a first programming level (L1).”).
Regarding claim 11, Lu discloses a memory device (FIG. 1B: memory device 130) comprising: a memory cell array (para. [0020]: “FIGS. 2A-2C are diagrams of portions of an example array of memory cells included in a memory device, . . .”); and a peripheral circuit coupled to the memory cell array and configured to perform a programming operation on the memory cell array (see FIG. 1B for various peripheral circuitry controlling the memory cell array 150), the programming operation comprising: programming memory cells of the memory cell array coupled to a first word line (para. [0023]: “. . . sequentially applying programming voltage pulses to a selected or target wordline (WLn).”); verifying whether the memory cells are programmed to a programming level of a plurality of programming levels (para. [0023]: “After each programming pulse, or after a number of programming pulses, a program verify operation can be performed to determine if the threshold voltage of the one or more memory cells has increased to a desired programming level.”), comprising: applying a verify voltage to the first word line (para. [0030]: “In a program verify operation, a read voltage is applied to the target wordline connected to the control gate of the selected memory cell.”); and applying a first pass voltage to one or more second word lines adjacent to the first word line (para. [0030]: “In addition, a program verify pass through voltage is applied to the wordlines connected to the control gates of the unselected memory cells.”; para. [0031]: “the program verify (PV) pass through voltage is applied to neighboring wordlines (e.g., WLn−1 and WLn+1) while the read voltage is applied to read the target wordline (WLn) to verify the programming state (e.g., whether the target wordline has reached the target programming level)”), wherein a value of the first pass voltage is lower than a value of a second pass voltage applied to the one or more second word lines when performing a read operation on the memory cells coupled to the first word line (para. [0033]: “During the read sub-operation, a program verify (PV) pass through voltage (herein referred to as the “PV pass voltage” or “Vpass(pv)”) is applied to the immediately adjacent or neighboring wordlines (WLn−1 and WLn+1) that has a voltage that is less than a pass through voltage applied to the neighboring wordlines in a read operation (Vpass(read))”).
Regarding claim 12, Lu discloses a programming level of the memory cells for verifying whether the memory cells are programmed to the programming level is equal to a programming level of the memory cells during the read operation of the memory cells (para. [0033]: “The program verify operation includes application of a program verify voltage level (Vpv) corresponding to a target programming level to the target wordline (WLn) to verify if programming at the target level is complete.”).
Regarding claim 13, Lu teaches verifying whether the memory cells are programmed to a programming level of a plurality of programming levels further comprises: applying a third pass voltage to remaining word lines of the memory device other than the first word line and the one or more second word lines, wherein a value of the third pass voltage is equal to a value of a fourth pass voltage applied to the remaining word lines when performing the read operation on the memory cells (para. [0026]: “It is noted that only one cell per bitline can be read at a time. Since the cells of a bitline are connected in series, all transistors for cells of the bitline that are not being read (“unread cells”) need to be kept on during the read operation in order for the read output of the read cell to pass through to the sense amplifier. To achieve this, a pass through voltage (Vpass) can be applied to the wordlines of the unread cells to keep the unread cells on.”—Official Notice: applying a pass voltage to each unselected word line to access data in a selected cell in either a verify or read operation is necessary in a string of NAND memory, and applying the same pass voltage to unselected word lines in a verify and read operation is common in the art (e.g. see Choi et al. (US 20250285689 A1) at para. [0052]; and Lee (US 20250087271 A1) at para. [0025])).
Regarding claim 14, Lu discloses the first pass voltage is determined based on the verify voltage of the first word line, a value of the first pass voltage decreases when a value of the verify voltage increases (FIG. 4A, para. [0035]: “”In this embodiment, the PV offset can incrementally increase as the corresponding target programming level of the target wordline increases. Accordingly, the PV offset increases as a function of the programming level (e.g., PV offset 1 for L1<PV offset 2 for L2<PV offset 3 for L3, and so on).”—Verify voltage is inherently proportional to the programming level (threshold voltage); therefore, Lu teaches the pass voltage decreases as the programming level and the corresponding required verify voltage to verify the programming level increase).
Regarding claim 15, Lu teaches the plurality of programming levels are sorted into a plurality of groups arranged in an ascending order, wherein a same value of the first pass voltage is applied when verifying programming levels in a same group, a lower value of the first pass voltage is applied when verifying programming levels in a group with higher order (para. [0035]: “Accordingly, the PV offset increases as a function of the programming level (e.g., PV offset 1 for L1<PV offset 2 for L2<PV offset 3 for L3, and so on). For example, the Vpass(pv) applied to WLn−1 and WLn+1 can be determined based on a first PV offset (e.g., PV offset 1) when the target wordline (WLn) is programmed to a first programming level (L1).”).
Regarding claim 20, Lu discloses a memory system (FIG. 1A: memory sub-system 110), comprising: a memory device (FIG. 1A: memory device 130); and a memory controller coupled to the memory device and configured to control the memory device (FIG. 1B: Local media controller 135), wherein the memory device comprises: a memory cell array (FIG. 1B: Array of memory cells 150); and a peripheral circuit coupled to the memory cell array and configured to perform a programming operation on the memory cell array (FIG. 1B: Column Decode 109, Row Decode 108, Address Register 114, Status Register 122, and Command Register 124), the programming operation comprising: programming memory cells coupled to a first word line (para. [0023]: “. . . sequentially applying programming voltage pulses to a selected or target wordline (WLn).”); verifying whether the memory cells are programmed to a programming level of a plurality of programming levels (para. [0023]: “After each programming pulse, or after a number of programming pulses, a program verify operation can be performed to determine if the threshold voltage of the one or more memory cells has increased to a desired programming level.”), comprising: applying a verify voltage to the first word line; and applying a first pass voltage to one or more second word lines adjacent to the first word line (para. [0030]: “In addition, a program verify pass through voltage is applied to the wordlines connected to the control gates of the unselected memory cells.”; para. [0031]: “the program verify (PV) pass through voltage is applied to neighboring wordlines (e.g., WLn−1 and WLn+1) while the read voltage is applied to read the target wordline (WLn) to verify the programming state (e.g., whether the target wordline has reached the target programming level)”), wherein a value of the first pass voltage is lower than a value of a second pass voltage applied to the one or more second word lines when performing a read operation on the memory cells coupled to the first word line (para. [0033]: “During the read sub-operation, a program verify (PV) pass through voltage (herein referred to as the “PV pass voltage” or “Vpass(pv)”) is applied to the immediately adjacent or neighboring wordlines (WLn−1 and WLn+1) that has a voltage that is less than a pass through voltage applied to the neighboring wordlines in a read operation (Vpass(read))”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 6-8 and 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (US 20240071530 A1; hereinafter "Lu") in view of Lee et al. (US 20220076761 A1; hereinafter "Lee").
Regarding claims 6-8 and 16-18, Lu discloses the method of operating a memory device and the memory device as set forth in the anticipation rejection of claims 1 and 11, respectively, above.
However, Lu does not teach determining an operating temperature of the memory device; and adjusting the value of the first pass voltage corresponding to the operating temperature; the value of the first pass voltage decreases when the operating temperature increases; nor the operating temperatures are sorted into a plurality of groups arranged in an ascending order, wherein a same value of the first pass voltage is applied when values of the operating temperatures are in a same group, a lower value of the first pass voltage is applied when values of the operating temperatures are in a group with higher order when verifying whether the memory cells are programmed to a same programming level of the plurality of programming levels.
Lee, in the same field of endeavor, discloses determining an operating temperature of the memory device; and adjusting the value of a pass voltage corresponding to the operating temperature (FIG. 8A, para. [0112]: “the magnitude of a pass voltage Vpass that is applied to unselected word lines WL1 to WLs−1 and WLs+1 to WLn depending on the temperature of the semiconductor memory device 100.”); and the value of the first pass voltage decreases when the operating temperature increases (FIG. 11B, and para. [0124]: “as the temperature rises, the magnitudes of both the first pass voltage Vpass1 and the second pass voltage Vpass2 decrease, whereas as the temperature falls, the magnitudes of both the first pass voltage Vpass1 and the second pass voltage Vpass2 increase.”).
Lee doesn’t explicitly teach sorting the operating temperatures into a plurality of groups arranged in an ascending order and applying pass voltages according to the plurality of groups; however, this limitation is interpreted as a design characteristic that would require only routine skill in the art to formulate. That is, Lee provides several graphs (e.g., FIGs. 8A and 11B) illustrating the continuous functional relationships between the memory device’s pass voltages and the memory device’s operating temperatures. A person having ordinary skill in the art would have known to group the operating temperatures in the plots into discrete segments associated with discrete pass voltage levels.
Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the method of operating the memory device and the memory device of Lu with the teachings of Lee. One of ordinary skill in the art would have been motivated to make this modification for the benefit of improving read performance depending on temperature changes (see Lee at para. [0004]).
Claim(s) 9 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (US 20240071530 A1; hereinafter "Lu") in view of Shin et al. (US 20220415419 A1; hereinafter "Shin").
Regarding claims 9 and 19, Lu discloses the method of operating a memory device and the memory device as set forth in the anticipation rejection of claims 1 and 11, respectively, above.
However, Lu does not disclose the value of the first pass voltage is further determined based on a quantity of program cycles of the memory cells, wherein the value of the first pass voltage increases when the quantity of program cycles increases.
Shin, in the same field of endeavor, discloses “the memory device 150 may apply an erase verification pass voltage having a higher level as an erase/write (E/W) cycle of a memory block increases” (see para. [0145]).
Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the method of operating the memory device and the memory device of Lu to increase a pass voltage as the programming (erase/write E/W) cycles increase. One of ordinary skill in the art would have been motivated to make this modification for the benefit of compensating for the amount of current that decreases as the E/W cycle increases (Shin at para. [0145]).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (US 20240071530 A1; hereinafter "Lu") .
Regarding claim 10, Lu discloses the method of operating a memory device and the memory device as set forth in the anticipation rejection of claims 1 and 11, respectively, above.
However, Lu does not disclose a specific minimum value of the first pass voltage (e.g. 5V).
Lu discloses,
“Since the cells of a bitline are connected in series, all transistors for cells of the bitline that are not being read (“unread cells”) need to be kept on during the read operation in order for the read output of the read cell to pass through to the sense amplifier. To achieve this, a pass through voltage (Vpass) can be applied to the wordlines of the unread cells to keep the unread cells on. More specifically, Vpass is a voltage that is chosen to be higher than all of the Vt's of the unread cells, but lower than a programming voltage, to ensure a memory cell is switched on. Although Vpass is a lower voltage than the programming voltage, the application of Vpass can affect (e.g., increase) the threshold voltage and thus alter logic states of the unread cells of the block via tunneling currents. This phenomenon is referred to as “read disturb.” As more read operations are applied within the block, the accumulation of read disturb over time can lead to read disturb errors.” (para. [0026]).
Thereby, teaching a minimum voltage of a pass voltage must be greater than any threshold voltage associated with any programming level of a memory cell to activate the channels of a plurality of memory cells connected to a single bit line during a read or verification operation without programming or disturbing any other memory cells. Under this principle, 5V must be within a range of valid pass voltages to reduce the likelihood read disturb and facilitate a read or verify operation and would have been known to a person having ordinary skill in the art to be a valid pass voltage within the parameters defined by Lu.
Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the method of operating the memory device and the memory device of Lu to set a minimum value of the first pass voltage greater than 5V. One of ordinary skill in the art would have been motivated to make this modification for the benefit of activating memory cells during a read/verify operation and prevent read disturb (Lu at para. [0026]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUSTIN BRYCE HEISTERKAMP whose telephone number is (703)756-1095. The examiner can normally be reached M-F 0800-1700.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUSTIN BRYCE HEISTERKAMP/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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