DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Response to Amendment
The amendment filed on 12/01/2025 has been considered by Examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 and 3 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Moon et al (US 2004/0165692 A1) in view of Yoon et al (US 2006/0139292 A1).
Claim 2, Moon (Fig. 5A-10) discloses a semiconductor device (Fig. 6; wherein discloses a shift register) comprising:
a first transistor (Q1; Fig. 6), a second transistor (Q2; Fig. 6), a third transistor (Q5; Fig. 6), a fourth transistor (MA; Fig. 6), a fifth transistor (MB; Fig. 6), a sixth transistor (Q6; Fig. 6), and a seventh transistor (Q3; Fig. 6),
wherein one of a source and a drain of the first transistor (Q1; Fig. 6) is electrically connected to a clock signal line (CKV; Fig. 6),
wherein the other of the source and the drain of the first transistor (Q1; Fig. 6) is electrically connected to an output signal line (GOUTn; Fig. 6),
wherein one of a source and a drain of the second transistor (Q2; Fig. 6) is electrically connected to a power supply line (VOFF; Fig. 6),
wherein the other of the source and the drain of the second transistor (Q2; Fig. 6) is electrically connected to the output signal line (GOUTn; Fig. 6),
wherein one of a source and a drain of the third transistor (Q5; Fig. 6) is electrically connected to the power supply line (VOFF; Fig. 6),
wherein the other of the source and the drain of the third transistor (Q5; Fig. 6) is electrically connected (N1; Fig. 6) to a gate of the first transistor (Q1; Fig. 6),
wherein a gate of the third transistor (Q5; Fig. 6) is electrically connected (N3; Fig. 6) to one of a source and a drain of the fourth transistor (MA; Fig. 6),
wherein the gate of the third transistor (Q5; Fig. 6) is electrically connected (N3; Fig. 6) to one of a source and a drain of the fifth transistor (MB; Fig. 6),
wherein a gate of the fourth transistor (MA; Fig. 6) is electrically connected to one of a source and a drain of the sixth transistor (Q6; Fig. 6),
wherein the other of the source and the drain of the fifth transistor (MB; Fig. 6) is electrically connected to the power supply line (VOFF; Fig. 6),
wherein a gate of the sixth transistor (Q6; Fig. 6) is electrically connected to a first signal line (VON; Fig. 6),
wherein one of a source and a drain of the seventh transistor (Q3; Fig. 7) is electrically connected to the first signal line (VON; Fig. 6),
wherein the other of the source and the drain of the seventh transistor (Q3; Fig. 7) is electrically connected (N1; Fig. 6) to the gate of the first transistor (Q1; Fig. 6),
wherein the other of the source and the drain of the seventh transistor (Q3; Fig. 7) is electrically connected (N1; Fig. 6) to the gate of the fifth transistor (MB; Fig. 6),
wherein a gate of the seventh transistor (Q3; Fig. 7) is electrically connected to a second signal line (GOUTn-1; Fig. 6),
wherein the second signal line (GOUTn-1; Fig. 6) is configured to supply a signal having high level and a low level (Fig. 3; wherein figure shows the gate signal GOUTn-1 which is received by the transistor Q3 in figure 7 to have both a high level (which enables the transistor Q3) and a low level (which disables the transistor Q3)),
wherein the fourth transistor (MA; Fig. 6; Paragraph [0052]) is configured to control a potential of the gate of the second transistor (Q2; Fig. 6) and control a potential of the gate of the third transistor (Q5; Fig. 6), and
wherein the sixth transistor (Q6; Fig. 6; Paragraph [0053]) is configured to control a potential of the gate of the fourth transistor (MA; Fig. 6).
Moon does not expressly disclose wherein the first signal line is configured to supply a signal having high level and low level.
Yoon (Fig. 1-11) discloses wherein the first signal line (VDD-o or VDD-e; Fig. 10; wherein figure show signal lines VDD-o and VDD-e respective connected to the gate electrodes of T3o1 and T3e1 which is similar to the claimed sixth transistor) is configured to supply a signal having high level and low level (Paragraph [0047]; wherein discloses “The odd source voltage "VDD-o" has a high level voltage during an odd frame and a low level voltage during an even frame. Contrarily, the even source voltage "VDD-e" has a low level voltage during an odd frame and a high level voltage during an even frame”; therefore the signal is alternating between a high level and low level as claimed).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Moon’s shift register by applying an alternating voltage source, as taught by Yoon, so to use a shift register with an alternating voltage source for improving the reliability of a shift register including one pull-down unit, a shift register including two pull-down units is suggested, where the variation in characteristics of TFTs such as the threshold voltage shift is be reduced (Paragraph [0038]).
Claim 3, Moon (Fig. 5A-10) discloses wherein the one of the source and the drain of the first transistor (Q1; Fig. 6) is directly connected to the clock signal line (CKV; Fig. 6),
wherein the other of the source and the drain of the first transistor (Q1; Fig. 6) is directly connected to the output signal line (GOUTn; Fig. 6),
wherein the one of the source and the drain of the second transistor (Q2; Fig. 6) is directly connected to the power supply line (VOFF; Fig. 6),
wherein the other of the source and the drain of the second transistor (Q2; Fig. 6) is directly connected to the output signal line (GOUTn; Fig. 6),
wherein the one of the source and the drain of the third transistor (Q5; Fig. 6) is directly connected to the power supply line (VOFF; Fig. 6),
wherein the gate of the third transistor (Q5; Fig. 6) is directly connected (N3; Fig. 6) to the one of the source and the drain of the fourth transistor (MA; Fig. 6),
wherein the gate of the third transistor (Q5; Fig. 6) is directly connected (N3; Fig. 6) to the one of the source and the drain of the fifth transistor (MB; Fig. 6),
wherein the gate of the fourth transistor (MA; Fig. 6) is directly connected to one of the source and the drain of the sixth transistor (Q6; Fig. 6),
wherein the other of the source and the drain of the fifth transistor (MB; Fig. 6) is directly connected to the power supply line (VOFF; Fig. 6),
wherein the gate of the sixth transistor (Q6; Fig. 6) is directly connected to the first signal line (VON; Fig. 6),
wherein the one of a source and a drain of the seventh transistor (Q3; Fig. 6) is directly connected to the first signal line (VON; Fig. 6),
wherein the other of the source and the drain of the seventh transistor (Q3; Fig. 6) is directly connected (N1; Fig. 6) to the gate of the fifth transistor (MB; Fig. 6), and
wherein the gate of the seventh transistor (Q3; Fig. 6) is directly connected to the second signal line (GOUTn-1; Fig. 6).
Claim 4 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Moon et al (US 2004/0165692 A1) in view of Yoon et al (US 2006/0139292 A1) as applied to claim 2 above, and further in view of Jeon et al (US 2004/0217935 A1).
Claim 4, Moon in view of Yoon discloses a semiconductor device according to claim 2.
Moon in view of Yoon does not expressly disclose wherein a W/L ratio of the first transistor, where W is a channel width and L is a channel length, is larger than a W/L ratio of the third transistor,
wherein the W/L ratio of the first transistor is larger than a W/L ratio of the fourth transistor,
wherein the W/L ratio of the first transistor is larger than a W/L ratio of the fifth transistor,
wherein the W/L ratio of the first transistor is larger than a W/L ratio of the sixth transistor, and
wherein the W/L ratio of the first transistor is larger than a W/L ratio of the seventh transistor.
Jeon (Fig. 1-12) discloses wherein a W/L ratio of the first transistor (NT1; Fig. 4), where W is a channel width (Paragraph [0043]; wherein discloses channel width 1110 micrometers) and L is a channel length (Paragraph [0043]; wherein discloses channel length 3.5 micrometers), is larger (Paragraph [0043]; 1110/3.5 is about 317) than a W/L ratio of the third transistor (NT10; Fig. 4; Paragraph [0049]; wherein discloses 150/3.5 is about 42),
wherein the W/L ratio of the first transistor (NT1; Fig. 4; Paragraph [0043]; 1110/3.5 is about 317) is larger than a W/L ratio of the fourth transistor (NT8; Fig. 4; Paragraph [0049]; wherein discloses 100/3.5 is about 28),
wherein the W/L ratio of the first transistor (NT1; Fig. 4; Paragraph [0043]; 1110/3.5 is about 317) is larger than a W/L ratio of the fifth transistor (NT9; Fig. 4; Paragraph [0049]; wherein discloses 150/3.5 is about 42),
wherein the W/L ratio of the first transistor (NT1; Fig. 4; Paragraph [0043]; 1110/3.5 is about 317) is larger than a W/L ratio of the sixth transistor (NT6; Fig. 4; Paragraph [0046]; wherein discloses 50/3.5 is about 14), and
wherein the W/L ratio of the first transistor (NT1; Fig. 4; Paragraph [0043]; 1110/3.5 is about 317) is larger than a W/L ratio of the seventh transistor (NT5; Fig. 4; Paragraph [0046]; wherein discloses 300/3.5 is about 85).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Moon in view of Yoon’s shift register by applying channel lengths and widths, as taught by Jeon, so to use a shift register with channel lengths and widths for providing a gate driving circuit having improved operational properties (Paragraph [0006]).
Claims 5 and 6 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Moon et al (US 2004/0165692 A1) in view of Yoon et al (US 2006/0139292 A1) and Lee et al (US 2003/0189542 A1).
Claim 5, Moon (Fig. 5A-10) discloses a semiconductor device (Fig. 6; wherein discloses a shift register) comprising:
a first transistor (Q1; Fig. 6), a second transistor (Q2; Fig. 6), a third transistor (Q5; Fig. 6), a fourth transistor (MA; Fig. 6), a fifth transistor (MB; Fig. 6), a sixth transistor (Q6; Fig. 6), and a seventh transistor (Q3; Fig. 6),
wherein one of a source and a drain of the first transistor (Q1; Fig. 6) is electrically connected to a clock signal line (CKV; Fig. 6),
wherein the other of the source and the drain of the first transistor (Q1; Fig. 6) is electrically connected to an output signal line (GOUTn; Fig. 6),
wherein one of a source and a drain of the second transistor (Q2; Fig. 6) is electrically connected to a power supply line (VOFF; Fig. 6),
wherein the other of the source and the drain of the second transistor (Q2; Fig. 6) is electrically connected to the output signal line (GOUTn; Fig. 6),
wherein one of a source and a drain of the third transistor (Q5; Fig. 6) is electrically connected to the power supply line (VOFF; Fig. 6),
wherein the other of the source and the drain of the third transistor (Q5; Fig. 6) is electrically connected (N1; Fig. 6) to a gate of the first transistor (Q1; Fig. 6),
wherein a gate of the third transistor (Q5; Fig. 6) is electrically connected (N3; Fig. 6) to one of a source and a drain of the fourth transistor (MA; Fig. 6),
wherein the gate of the third transistor (Q5; Fig. 6) is electrically connected (N3; Fig. 6) to one of a source and a drain of the fifth transistor (MB; Fig. 6),
wherein a gate of the fourth transistor (MA; Fig. 6) is electrically connected to one of a source and a drain of the sixth transistor (Q6; Fig. 6),
wherein the other of the source and the drain of the fifth transistor (MB; Fig. 6) is electrically connected to the power supply line (VOFF; Fig. 6),
wherein a gate of the sixth transistor (Q6; Fig. 6) is electrically connected to a first signal line (VON; Fig. 6),
wherein one of a source and a drain of the seventh transistor (Q3; Fig. 7) is electrically connected to the first signal line (VON; Fig. 6),
wherein the other of the source and the drain of the seventh transistor (Q3; Fig. 7) is electrically connected (N1; Fig. 6) to the gate of the first transistor (Q1; Fig. 6),
wherein the other of the source and the drain of the seventh transistor (Q3; Fig. 7) is electrically connected (N1; Fig. 6) to the gate of the fifth transistor (MB; Fig. 6),
wherein a gate of the seventh transistor (Q3; Fig. 7) is electrically connected to a second signal line (GOUTn-1; Fig. 6),
wherein the second signal line (GOUTn-1; Fig. 6) is configured to supply a signal having high level and a low level (Fig. 3; wherein figure shows the gate signal GOUTn-1 which is received by the transistor Q3 in figure 7 to have both a high level (which enables the transistor Q3) and a low level (which disables the transistor Q3)),
wherein the fourth transistor (MA; Fig. 6; Paragraph [0052]) is configured to control a potential of the gate of the second transistor (Q2; Fig. 6) and control a potential of the gate of the third transistor (Q5; Fig. 6), and
wherein the sixth transistor (Q6; Fig. 6; Paragraph [0053]) is configured to control a potential of the gate of the fourth transistor (MA; Fig. 6).
Moon does not expressly disclose wherein the first signal line is configured to supply a signal having high level and low level.
Yoon (Fig. 1-11) discloses wherein the first signal line (VDD-o or VDD-e; Fig. 10; wherein figure show signal lines VDD-o and VDD-e respective connected to the gate electrodes of T3o1 and T3e1 which is similar to the claimed sixth transistor) is configured to supply a signal having high level and low level (Paragraph [0047]; wherein discloses “The odd source voltage "VDD-o" has a high level voltage during an odd frame and a low level voltage during an even frame. Contrarily, the even source voltage "VDD-e" has a low level voltage during an odd frame and a high level voltage during an even frame”; therefore the signal is alternating between a high level and low level as claimed).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Moon’s shift register by applying an alternating voltage source, as taught by Yoon, so to use a shift register with an alternating voltage source for improving the reliability of a shift register including one pull-down unit, a shift register including two pull-down units is suggested, where the variation in characteristics of TFTs such as the threshold voltage shift is be reduced (Paragraph [0038]).
Moon in view of Yoon does not expressly disclose an eighth transistor,
wherein one of a source and a drain of the eighth transistor is electrically connected to the power supply line,
wherein the other of the source and the drain of the eighth transistor is electrically connected to the output signal line,
wherein a gate of the eighth transistor is electrically connected to a third signal line,
wherein the third signal line is configured to supply a signal having high level and low level.
Lee (Fig. 1-3) discloses an eighth transistor (NT13; Fig. 3),
wherein one of a source and a drain of the eighth transistor (NT13; Fig. 3) is electrically connected to the power supply line (VSST; Fig. 3),
wherein the other of the source and the drain of the eighth transistor (NT13; Fig. 3) is electrically connected to the output signal line (OUT; Fig. 3),
wherein a gate of the eighth transistor (NT13; Fig. 3) is electrically connected to a third signal line (CT; Fig. 3),
wherein the third signal line (CT; Fig. 2; wherein figure shows terminal CT is the output signal from the next stage; Fig. 11; wherein figure shows output signals (OUT2 for example) having a high level VH and a low level VL) is configured to supply a signal having high level and low level (Fig. 11; wherein figure shows output signals (OUT2 for example) having a high level VH (Paragraph [0060]) and a low level VL).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Moon in view of Yoon’s shift register by applying an eight transistor, as taught by Lee, so to use a shift register with an eight transistor for providing a driver circuit for driving an active matrix driving display device for the purpose of enhancing the display quality of the display device (Paragraph [0012]).
Claim 6, Moon (Fig. 5A-10) discloses wherein the one of the source and the drain of the first transistor (Q1; Fig. 6) is directly connected to the clock signal line (CKV; Fig. 6),
wherein the other of the source and the drain of the first transistor (Q1; Fig. 6) is directly connected to the output signal line (GOUTn; Fig. 6),
wherein the one of the source and the drain of the second transistor (Q2; Fig. 6) is directly connected to the power supply line (VOFF; Fig. 6),
wherein the other of the source and the drain of the second transistor (Q2; Fig. 6) is directly connected to the output signal line (GOUTn; Fig. 6),
wherein the one of the source and the drain of the third transistor (Q5; Fig. 6) is directly connected to the power supply line (VOFF; Fig. 6),
wherein the gate of the third transistor (Q5; Fig. 6) is directly connected (N3; Fig. 6) to the one of the source and the drain of the fourth transistor (MA; Fig. 6),
wherein the gate of the third transistor (Q5; Fig. 6) is directly connected (N3; Fig. 6) to the one of the source and the drain of the fifth transistor (MB; Fig. 6),
wherein the gate of the fourth transistor (MA; Fig. 6) is directly connected to one of the source and the drain of the sixth transistor (Q6; Fig. 6),
wherein the other of the source and the drain of the fifth transistor (MB; Fig. 6) is directly connected to the power supply line (VOFF; Fig. 6),
wherein the gate of the sixth transistor (Q6; Fig. 6) is directly connected to the first signal line (VON; Fig. 6),
wherein the one of a source and a drain of the seventh transistor (Q3; Fig. 6) is directly connected to the first signal line (VON; Fig. 6),
wherein the other of the source and the drain of the seventh transistor (Q3; Fig. 6) is directly connected (N1; Fig. 6) to the gate of the fifth transistor (MB; Fig. 6), and
wherein the gate of the seventh transistor (Q3; Fig. 6) is directly connected to the second signal line (GOUTn-1; Fig. 6).
Lee (Fig. 1-3) discloses wherein the one of the source and the drain of the eighth transistor (NT13; Fig. 3) is directly connected to the power supply line (VSST; Fig. 3),
wherein the other of the source and the drain of the eighth transistor (NT13; Fig. 3) is directly connected to the output signal line (OUT; Fig. 13), and
wherein the gate of the eighth transistor (NT13; Fig. 3) is directly connected to the third signal line (CT; Fig. 3).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Moon in view of Yoon’s shift register by applying an eight transistor, as taught by Lee, so to use a shift register with an eight transistor for providing a driver circuit for driving an active matrix driving display device for the purpose of enhancing the display quality of the display device (Paragraph [0012]).
Claim 7 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Moon et al (US 2004/0165692 A1) in view of Yoon et al (US 2006/0139292 A1) and Lee et al (US 2003/0189542 A1) as applied to claim 5 above, and further in view of Jeon et al (US 2004/0217935 A1).
Claim 7, Moon in view of Yoon and Lee discloses a semiconductor device according to claim 5.
Moon in view of Yoon and Lee does not expressly disclose wherein a W/L ratio of the first transistor, where W is a channel width and L is a channel length, is larger than a W/L ratio of the third transistor,
wherein the W/L ratio of the first transistor is larger than a W/L ratio of the fourth transistor,
wherein the W/L ratio of the first transistor is larger than a W/L ratio of the fifth transistor,
wherein the W/L ratio of the first transistor is larger than a W/L ratio of the sixth transistor, and
wherein the W/L ratio of the first transistor is larger than a W/L ratio of the seventh transistor.
Jeon (Fig. 1-12) discloses wherein a W/L ratio of the first transistor (NT1; Fig. 4), where W is a channel width (Paragraph [0043]; wherein discloses channel width 1110 micrometers) and L is a channel length (Paragraph [0043]; wherein discloses channel length 3.5 micrometers), is larger (Paragraph [0043]; 1110/3.5 is about 317) than a W/L ratio of the third transistor (NT10; Fig. 4; Paragraph [0049]; wherein discloses 150/3.5 is about 42),
wherein the W/L ratio of the first transistor (NT1; Fig. 4; Paragraph [0043]; 1110/3.5 is about 317) is larger than a W/L ratio of the fourth transistor (NT8; Fig. 4; Paragraph [0049]; wherein discloses 100/3.5 is about 28),
wherein the W/L ratio of the first transistor (NT1; Fig. 4; Paragraph [0043]; 1110/3.5 is about 317) is larger than a W/L ratio of the fifth transistor (NT9; Fig. 4; Paragraph [0049]; wherein discloses 150/3.5 is about 42),
wherein the W/L ratio of the first transistor (NT1; Fig. 4; Paragraph [0043]; 1110/3.5 is about 317) is larger than a W/L ratio of the sixth transistor (NT6; Fig. 4; Paragraph [0046]; wherein discloses 50/3.5 is about 14), and
wherein the W/L ratio of the first transistor (NT1; Fig. 4; Paragraph [0043]; 1110/3.5 is about 317) is larger than a W/L ratio of the seventh transistor (NT5; Fig. 4; Paragraph [0046]; wherein discloses 300/3.5 is about 85).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Moon in view of Yoon and Lee’s shift register by applying channel lengths and widths, as taught by Jeon, so to use a shift register with channel lengths and widths for providing a gate driving circuit having improved operational properties (Paragraph [0006]).
Response to Arguments
Applicant's arguments with respect to claims 2-7 have been considered but are moot in view of the new ground(s) of rejection.
In view of arguments, the references of Moon et al (US 2004/0165692 A1), Yoon et al (US 2006/0139292 A1), Lee et al (US 2003/0189542 A1), and Jeon et al (US 2004/0217935 A1) have been used for new ground rejection.
Claims 2 and 5 are rejected in view of newly discovered reference(s) to Yoon et al (US 2006/0139292 A1). Wherein cited reference of Yoon et al (US 2006/0139292 A1) is cited to teach a voltage source (VDD-o or VDD-e; Fig. 10) that alternates from a high level to low level (Paragraph [0047]) that is applied to the gate electrode of the sixth transistor (T3o1 or T3e1; Fig. 10).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM J SNYDER whose telephone number is (571)270-3460. The examiner can normally be reached Monday-Friday 8am-4:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh D Nguyen can be reached at (571)272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Adam J Snyder/Primary Examiner, Art Unit 2623 02/12/2026
Prosecution Insights