DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim(s) 1-2, 9, 11, 15, 18 and 20 are rejected under 35 U.S.C. 102(a1).
Claim(s) 3-8, 10, 12-14, 16-17 and 19 are rejected under 35 U.S.C. 103.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 9, 11, 15, 18 and 20 are rejected under 35 U.S.C. 102(a1) as being anticipated by US Patent 12,276,490 to Vaez-Iravani et al.
In regards to claims 1-2, 9 and 11, Vaez-Iravani discloses and shows in Figures 1-6, a semiconductor process apparatus (col. 1, ll. 23-44), comprising:
a stage (110) on which a substrate (202) including a photoresist layer is configured to be seated (col. 4, ll. 1-68; col. 7, ll. 51-62; wherein a robot transport blade or a processing chamber stage may support the wafer);
a light source (112, 204) configured to irradiate a pulse of light toward the substrate (col. 4, ll. 1-68; col. 7, ll. 51-62; wherein a plurality of light sources may be utilized) (col. 8, ll. 1-12; wherein a pulsed light source may be utilized);
a sensor (114, 206) configured to generate an output signal in response to reflected light reflected from the substrate (col. 4, ll. 1-68; col. 7, ll. 51-62; wherein a plurality of optical sensors may be utilized); and
a controller (118, 122, 124) configured to control the light source and the sensor and to measure the photoresist layer using the output signal (col. 5, ll. 1-8; wherein a general computer with a plurality of control modules may be utilized),
wherein the controller is configured to obtain, from the output signal, a first output signal corresponding to a first beam of the reflected light reflected from a surface of the photoresist layer and a second output signal corresponding to a second beam of the reflected light reflected from a region below a surface of the photoresist layer, and to measure the photoresist layer using the first output signal and the second output signal (col. 6, ll. 22 to col. 7, ll. 50; wherein a plurality of intensity values, which are generated by interference from a beam reflected at a top surface of the substrate and a lower surface of the substrate, are obtained by a plurality of beams reflected from a plurality of scanned locations) (col. 8, ll. 1-31; wherein interference is generated from multiple internal reflections within a substrate, and wherein the spatial frequency of the interference allows a thickness profile of the substrate to be generated);
[claim 2] wherein the controller is configured to determine a surface profile of the photoresist layer using a difference between an intensity of the first output signal and an intensity of the second output signal (col. 2, ll. 9-31; col. 6, ll. 22-32; col. 8, ll. 1-31; wherein interference is generated from multiple internal reflections within a substrate, and wherein the spatial frequency of the interference allows a thickness profile of the substrate to be generated);
[claim 9] wherein the light source is configured to irradiate the pulse of light in a visible wavelength range (col. 4, ll. 22-44);
[claim 11] wherein an incident angle of the pulse of light to a surface of the photoresist layer is 75 degrees or less (Figures 2a-c) (col. 7, ll. 24-50; wherein the light beams may have a variable angle of incidence onto a substrate).
In regards to claims 15 and 18, Vaez-Iravani discloses and shows in Figures 1-6, a semiconductor process apparatus (col. 1, ll. 23-44), comprising:
a stage (110) on which a substrate (202) including a photoresist layer is configured to be seated (col. 4, ll. 1-68; col. 7, ll. 51-62; wherein a robot transport blade or a processing chamber stage may support the wafer);
a light source (112, 204) configured to irradiate a pulse of light having a predetermined duration in each of a plurality of target regions defined along a direction parallel to a surface of the substrate (col. 4, ll. 1-68; col. 7, ll. 51-62; wherein a plurality of light sources may be utilized) (col. 8, ll. 1-31; wherein a pulsed light source may be utilized to illuminate a plurality of locations in a desired scanning pattern);
a sensor (114, 206) configured to generate an output signal in response to reflected light reflected from the substrate (col. 4, ll. 1-68; col. 7, ll. 51-62; col. 8, ll. 1-31; wherein a plurality of optical sensors may be utilized to obtain a plurality of beams from a plurality of locations on a substrate); and
a controller (118, 122, 124) configured to control the light source and the sensor and to measure the photoresist layer using the output signal (col. 5, ll. 1-8; wherein a general computer with a plurality of control modules may be utilized),
a controller configured to obtain, from an output signal generated by the sensor in response to the reflected light, a first output signal corresponding to a first beam of the reflected light reflected from a surface of the photoresist layer in each of the plurality of target regions, and wherein the controller is configured to measure a surface profile of the photoresist layer based on the first output signal. (col. 6, ll. 22 to col. 7, ll. 50; wherein a plurality of intensity values, which are generated by interference from a beam reflected at a top surface of the substrate and a lower surface of the substrate, are obtained by a plurality of beams reflected from a plurality of scanned locations) (col. 8, ll. 1-31; wherein interference is generated from multiple internal reflections within a substrate, and wherein the spatial frequency of the interference allows a thickness profile of the substrate to be generated);
[claim 18] wherein the controller is configured to obtain the first output signal from the output signal based on at least one of a time point at which the first output signal is generated and an intensity of the first output signal (col. 6, ll. 22 to col. 7, ll. 50; wherein a plurality of intensity values, which are generated by interference from a beam reflected at a top surface of the substrate and a lower surface of the substrate, are obtained by a plurality of beams reflected from a plurality of scanned locations).
In regards to claim 20, Vaez-Iravani discloses and shows in Figures 1-6, a semiconductor process apparatus (col. 1, ll. 23-44), comprising:
a stage (110) on which a substrate (202) including a photoresist layer is configured to be seated (col. 4, ll. 1-68; col. 7, ll. 51-62; wherein a robot transport blade or a processing chamber stage may support the wafer);
a light source (112, 204) configured to irradiate a pulse of light toward the substrate (col. 4, ll. 1-68; col. 7, ll. 51-62; wherein a plurality of light sources may be utilized) (col. 8, ll. 1-12; wherein a pulsed light source may be utilized);
a sensor (114, 206) configured to generate an output signal in response to reflected light reflected from the substrate (col. 4, ll. 1-68; col. 7, ll. 51-62; wherein a plurality of optical sensors may be utilized); and
a controller (118, 122, 124) configured to control the light source and the sensor and to measure the photoresist layer using the output signal (col. 5, ll. 1-8; wherein a general computer with a plurality of control modules may be utilized),
wherein the controller is configured to distinguish between a first output signal and a second output signal, the first output signal corresponding to a first beam of the reflected light directly reflected from the surface of the substrate, and the second output signal corresponding to a second beam of the reflected light traveling to a region below the surface of the substrate and reflected, wherein the controller is further configured to measure a surface profile of the substrate using the first output signal (col. 6, ll. 22 to col. 7, ll. 50; col. 8, ll. 1-31; wherein a thickness profile of a substrate may be generated by a plurality of intensity values, which are generated by interference from a beam reflected at a top surface of the substrate and a lower surface of the substrate, and wherein the values may be determined from a plurality of different beams at a plurality of different locations, wherein the beams may have different wavelengths and/or angles of incidence onto the substrate).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3-8 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Vaez-Iravani, in view of US Publication 2020/0103526 to Morcom.
In regards to claims 3-6 and 16, Vaez-Iravani differs from the limitations in that it is silent to the semiconductor process apparatus,
[claim 3] wherein the controller is configured to determine a surface profile of the photoresist layer using a time difference between a time point at which the first output signal is generated and a time point at which the second output signal is generated;
[claim 4] wherein the controller is configured to set a duration of the pulse of light based on a thickness of the photoresist layer;
[claim 5] wherein the sensor is a time-of-flight (ToF) sensor;
[claim 6] wherein the sensor includes a plurality of photodiodes arranged in one direction;
[claim 16] wherein the sensor includes a photodiode (PD) array including a plurality of photodiodes arranged therein, and wherein the controller is configured to set an area of each of the plurality of target regions based on a field of view (FOV) of the PD array.
However, Morcom teaches and shows in Figures 1 and 6, a time-of-flight (ToF) distance sensor, wherein a remote object is illuminated with a pulsed fan beam (4) (par. 14, 57) and a one-dimensional array of pixels receive a reflected line beam from a field of view of the fan beam (par. 2-5, 8, 58). Morcom further teaches the ToF system wherein the temporal characteristics of the light pulse are controlled based on a desired range and resolution (par. 56; wherein the range of the system may be considered the thickness of the layer), and the system utilizes a clock controller to detect the reflected pulses (applicant’s time points) and determine a surface profile and range to an object (12) (par. 5, 18, 62, 69).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention, to modify Vaez-Iravani to include the time-of-flight and clocking system discussed above for the advantage of providing fast and accurate profile and range measurements (par. 2), with a reasonable expectation of success.
In regards to claims 7-8, Vaez-Iravani discloses the semiconductor process apparatus, [claim 7] wherein the controller is configured to drive the light source such that the pulse of light is irradiated to each of a plurality of target regions, and to measure the photoresist layer using the first output signal and the second output signal generated by the sensor for each of the plurality of target regions, and wherein the plurality of target regions are disposed along directions parallel to a surface of the substrate (col. 2, ll. 61-65; col. 6, ll. 22-55; col. 8, ll. 13-31; col. 13, ll. 58-68; wherein the surface of the substrate may be scanned in various desired patterns, such as spiral, rectangular, zigzag, “or any other geometric pattern”);
[claim 8] wherein each of the plurality of target regions is defined to extend in one direction, and a length of each of the plurality of target regions is less than a maximum length of the substrate in the one direction (col. 2, ll. 61-65; col. 6, ll. 22-55; col. 8, ll. 13-31; col. 13, ll. 58-68; wherein the surface of the substrate may be scanned in various desired patterns, such as spiral, rectangular, zigzag, “or any other geometric pattern”) (Figures 2a-c).
Claim(s) 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Vaez-Iravani, in view of US Patent 5,526,093 to Takahashi.
In regards to claims 12-14, Vaez-Iravani discloses and shows in Figure 1, a semiconductor process apparatus, further comprising:
a first working space (102, 104) in which the stage (110) and the light source (112) are disposed (col. 3, ll. 60 to col. 4, ll. 68; wherein a manufacturing system is shown to have a loading station 102, a transfer chamber 104, and a plurality of processing chambers 106, and wherein the light sources and sensors may be positioned in any of the different chambers);
a second working space (106) separated from the first working space (col. 3, ll. 60 to col. 4, ll. 68; wherein a manufacturing system is shown to have a loading station 102, a transfer chamber 104, and a plurality of processing chambers 106, and wherein the light sources and sensors may be positioned in any of the different chambers);
[claim 13] wherein the controller is configured to move the substrate to the substrate stage when the measurement of the photoresist layer is completed and a surface profile of the photoresist layer passes a predetermined criterion (col. 3, ll. 60 to col. 4, ll. 68; wherein a substrate may be transported through a variety of different processing chambers) (col. 12, ll. 11-52; col. 15, ll. 6-15; wherein the thickness profile of the substrate may be continuously monitored to determine when desired processing criteria have been meet);
[claim 14] wherein the controller is configured to perform a process of forming the photoresist layer again when the measurement of the photoresist layer is completed and a surface profile of the photoresist layer does not pass a predetermined criterion (col. 3, ll. 60 to col. 4, ll. 68; wherein a substrate may be transported through a variety of different processing chambers) (col. 12, ll. 11-52; col. 15, ll. 6-15; wherein the thickness profile of the substrate may be continuously monitored to determine when desired processing criteria have been meet or whether further processing is necessary).
Vaez-Iravani differs from the limitations in that it is silent to the system further comprising:
a second light source installed in the second working space and configured to output light of a specific wavelength band;
a mask stage on which a mask configured to reflect or transmit light is seated;
a substrate stage to which light reflected from or transmitted through the mask is irradiated;
an illumination optical system configured to transmit light between the second light source and the mask stage; and
a projection optical system configured to transmit light between the mask stage and the substrate stage.
However, Takahashi teaches and shows in Figure 1, an exposure system and method for manufacturing semiconductor devices comprising: a light source (1) (applicant’s second light source), a reticle stage (44) and reticle (7) (applicant’s mask stage and mask), an imaging lens (6) (applicant’s illumination optical system), a projection optical system (8) (applicant’s projection system), and a wafer stage (42) (applicant’s substrate stage) (col. 3, ll. 9-68). Further, semiconductor exposure systems, comprising the elements discussed above, are well-known to those of ordinary skill in the art.
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention, to modify Vaez-Iravani to include the semiconductor exposure system discussed above for the advantage of utilizing a well-known system to quickly and accurately manufacture semiconductor devices onto a wafer, with a reasonable expectation of success.
Claim(s) 10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Vaez-Iravani and Morcom, in view of US Publication 2010/0259744 to Van Herpen et al.
In regards to claims 10 and 17, Vaez-Iravani and Morcom differ from the limitations in that they are silent to the semiconductor process apparatus, further comprising:
[claim 10] a grid structure disposed in a path on which the reflected light is configured to travel to the sensor, wherein a change in intensity of the first beam of reflected light due to the grid structure is smaller than a change in an intensity of the second beam of reflected light due to the grid structure;
[claim 17] further comprising: a grid structure disposed in a path on which the reflected light travels, the grid structure having a slit through which the reflected light passes, wherein an intensity at which the first beam of the reflected light passes through the slit is stronger than an intensity at which a second beam of the reflected light not reflected from the surface of the photoresist layer passes through the slit.
However, Van Herpen teaches and shows in Figures 1-4, a lithographic system and method wherein a plurality of spectral filters (101, 102) (applicant’s grid structure) may be utilized, including a slit or grating stricture (104, 105, 204, 205), to enhance spectral purity by blocking unwanted radiation and transmitting desired radiation (par. 89).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention, to modify Vaez-Iravani and Morcom to include the slit or grid structure discussed above for the advantage of enhancing spectral purity by blocking transmission of undesired light, with a reasonable expectation of success.
Claim(s) 19 is rejected under 35 U.S.C. 103 as being unpatentable over Vaez-Iravani, in view of US Publication 2024/0077302 to Adler.
In regards to claim 19, Vaez-Iravani differs from the limitations in that it is silent to the semiconductor process apparatus, wherein the predetermined duration is in a range from several femtoseconds to several picoseconds.
However, Adler teaches and shows in Figure 8a-b and 21, a metrology system and method, wherein a commercially available short pulsed light source, femtosecond or picosecond, may be utilized to provide desired peak power, wavelength and reliability (par. 30, 128, 130).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention, to modify Vaez-Iravani to include the short-pulsed light source discussed above for the advantage of utilizing a commercially available light source to provide a desired peak power, wavelength and reliability, with a reasonable expectation of success.
Conclusion
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JONATHAN M. HANSEN
Primary Examiner
Art Unit 2877
/JONATHAN M HANSEN/Primary Examiner, Art Unit 2877
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