DETAILED ACTION
This action is responsive to the response filed 14 Jan 2025. Claims 1-20 are pending. Claims 1, 17 and 18 are independent.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 2 and 5 is/are objected to because of the following informalities:
Claim 2 and 5 have the following limitation: “in response to determining the portion is unavailable for writing data, applying both inner WL offset values and boundary WL offset values to read the one or more WLs of the portion of the memory device.” This limitation requires that both the inner WLs (regardless of their proximity to the boundary WL) and the boundary (regardless to their proximity to any programmed lines) offsets be applied to each WL selected for a “read” operation within the “closed” portion of a memory by adjusting for both the inner WL or a boundary WL offset values. It’s possible that applicant intended to adjust for either the inner WL or the boundary WL depending on proximity in the memory block.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claims 1, 17 and 18, recites the limitation, “in response to receiving the request to read the data, determining whether the portion of the memory device is available for writing data; and.” And later recites the limitation, “selectively applying boundary word line (WL) offset values to read one or more WLs of the portion of the memory device” This claim is indefinite because the cited “portion” can comprise at least two WLs, a 1st WL in the portion might be “available for writing” and 2nd WL in the portion might not be “available for writing”. Applicant might consider altering the language to address “one or more WLs available for writing”, or words that recognize the “portion” addressed may not be homogenous.
Claims 1, 17 and 18 recites the limitation, ““selectively applying boundary WL offset values to read one or more WLs of the portion of the memory device in addition to applying inner WL offset values IN RESPONSE to determining whether the portion of the memory device is available for writing data” As written, it is indefinite as to whether the “selected.. one or more WLs” should have either the boundary WL offset value applied, the inner WL offset value applied, or if both must be applied.
Claim 4 recites the limitation, “reading data from the portion of the memory device using at least one of the inner WL offset values or the boundary WL offset values.” As stated above, claim 1 language states that both the “boundary word line offset value”… “in addition to applying inner WL offset values” must be applied. A dependent claim cannot subtract, or remove actions taken by the independent claim.
Claim 8 recites the limitation, “reading the data using only the inner WL offset values in response to determining that the portion comprises the open memory block.” Per applicant’s specification, an “open memory block” comprises portions that are “available for writing”. As stated above, claim 1 language states that both the “boundary word line offset value”… “in addition to applying inner WL offset values” must be applied. A dependent claim cannot subtract, or remove actions taken by the independent claim.
Claim 20 recites the limitation, “in response to determining the portion is available for writing data, applying the inner WL offset values without boundary WL offset values to read one or more WLs”. As stated above, claim 18 language states that both the “boundary word line offset value”… “in addition to applying inner WL offset values” must be applied. A dependent claim cannot subtract, or remove actions taken by the independent claim.
Claim(s) 2-16 and 19-20 depend on rejected claim(s) 1 and 18 and are also rejected under 35 U.S.C. 112(b).
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless —
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 3, 4, 8, 9, and 15 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang, et al, U.S. Patent Application Publication 2023/0393991 (“Chang”).
Regarding claim 1, Chang teaches:
A system comprising: a memory device; and a processing device, operatively coupled to the memory device, configured to perform operations comprising: (Chang, fig 8, “[0087] FIG. 8 illustrates an example machine of a computer system 800 within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, can be executed. [0097] A machine- readable medium includes any mechanism for storing information in a form readable by a machine.”; a memory device with host and sub-system processors which execute programming instructions stored in a mechanism).
receiving a request to read data from a portion of the memory device; in response to receiving the request to read the data, determining whether the portion of the memory device is available for writing data; and (Chang, fig 1, 6, 8, “[0070] At operation 610, the processing logic receives a read command specifying a logical address. The processing logic can receive the read command from a host system, such as host system 120 of FIG. 1. [0072] At operation 630, responsive to determining that the physical block is partially programmed, the processing logic identifies a threshold voltage offset associated with the wordline. [0019] A partially programmed block (or a partial block) refers to a block in which not every wordline has been programmed. The most recently programmed wordline can be referred to as the boundary wordline. The wordlines following the boundary wordline are not programmed; that is, the cells connected to the wordlines following the boundary wordline are in an erase state.”; a device which first receives a read command, the device checks if the target block is partially programmed (with erased word lines, which are available for writing.)).
selectively applying boundary word line (WL) offset values to read one or more WLs of the portion of the memory device in addition to applying inner WL offset values in response to determining whether the portion of the memory device is available for writing data. (Chang, fig 5, 6, “[0065] The memory sub-system controller 115 can maintain multiple additional sub-BFEA offset tables 506, each one associated with one or more parameters… whether the data is stored in a boundary wordline or an inner wordline. [0067] The adaptive BFEA component 113 can then identify the appropriate additional sub-BFEA offset table 506 based on the sub-BFEA parameters, such as the value of a media state metric ( e.g., the number of program/erase cycles performed on the memory device), whether the data is stored in a boundary wordline or an inner wordline, the difference between the boundary wordline and the wordline storing the data, and/or the wordline group of the wordline. [0068] The adaptive BFEA component 113 can then additively apply the identified threshold voltage offset to the base voltage read level in order to perform the requested read operation.”; using the conditions of the word line to select the correct read voltage offset based on the: WL residing in a partially programmed ‘portion of the memory device”; and the location within the block; at the boundary WL both the table 504 and one or more tables 506 for data stored in a “boundary WL or an inner WL” offset can be added to arrive at the adaptive offset. Note: a “portion” of a memory device could be one word line).
Regarding claim 3, Chang teaches The system of claim 1, wherein the portion is determined to be available for writing data in response to determining that the portion comprises an open memory block, wherein the portion is determined to be unavailable for writing data in response to determining that the portion comprises a closed memory block. (Chang, fig 1, 6, “[0025] These threshold voltage shift phenomena can affect partially programmed blocks differently than they affect fully programmed blocks. [0072] The full block indicator can be stored in metadata of the physical block. For example, the full block indicator can be a binary flag, with a value of “0” to indicate that the corresponding block is partially programmed, and a value of “l” to indicate that that the corresponding block is fully programmed.”; a block can be identified as fully programmed (i.e. closed) or partially programmed (i.e. open) Note: open and closed blocks are defined in applicant’s specification paragraph 0014).
Regarding claim 4, Chang teaches:
The system of claim 3, the operations comprising: accessing tracking information in response to receiving the request, the tracking information indicating whether the portion is available or unavailable for writing the data; and (Chang, fig 1, 6, “[0025] These threshold voltage shift phenomena can affect partially programmed blocks differently than they affect fully programmed blocks. [0072] The full block indicator can be stored in metadata of the physical block. For example, the full block indicator can be a binary flag, with a value of “0” to indicate that the corresponding block is partially programmed, and a value of “l” to indicate that that the corresponding block is fully programmed.”; a block can be identified (i.e. tracked) as fully programmed (i.e. closed) or partially programmed (i.e. open) Note: open and closed blocks are defined in applicant’s specification paragraph 0014).
reading data from the portion of the memory device using at least one of the inner WL offset values or the boundary WL offset values. (Chang, fig 5, 6, “[0067] The adaptive BFEA component 113 can then identify the appropriate additional sub-BFEA offset table 506 based on the sub-BFEA parameters, such as the value of a media state metric ( e.g., the number of program/erase cycles performed on the memory device), whether the data is stored in a boundary wordline or an inner wordline, the difference between the boundary wordline and the wordline storing the data, and/or the wordline group of the wordline. [0068] The adaptive BFEA component 113 can then additively apply the identified threshold voltage offset to the base voltage read level in order to perform the requested read operation.”; using the conditions of the word line to select the correct read voltage offset based on the: WL residing in a partially programmed ‘portion of the memory device”; and the location within the block; at the boundary WL both the table 504 and table 506 “boundary WL and inner WL” offsets can be added to arrive at the adaptive offset. Note: the claim as written does not assign a particular system to use either the inner, boundary WL offset, or both).
Regarding claim 8, Chang teaches The system of claim 4, the operations comprising: reading the data using only the inner WL offset values in response to determining that the portion comprises the open memory block. (Chang, fig 5, 6, “[0065] The memory sub-system controller 115 can maintain multiple additional sub-BFEA offset tables 506, each one associated with one or more parameters… whether the data is stored in a boundary wordline or an inner wordline. [0067] The adaptive BFEA component 113 can then identify the appropriate additional sub-BFEA offset table 506 based on the sub-BFEA parameters, such as the value of a media state metric ( e.g., the number of program/erase cycles performed on the memory device), whether the data is stored in a boundary wordline or an inner wordline, the difference between the boundary wordline and the wordline storing the data, and/or the wordline group of the wordline. [0068] The adaptive BFEA component 113 can then additively apply the identified threshold voltage offset to the base voltage read level in order to perform the requested read operation.”; using the conditions of the word line to select the correct read voltage offset based on the: WL residing in a partially programmed ‘portion of the memory device”; and the location within the block; at the boundary WL both the table 504 and one or more tables 506 for data stored in a “boundary WL or an inner WL” offset can be added to arrive at the adaptive offset; Change teaches using a table 506 for inner WL only. Note: a “portion” of a memory device could be one word line).
Regarding claim 9, Chang teaches:
The system of claim 1, wherein the portion comprises a plurality of WLs, the plurality of WLs comprising one or more inner WLs including an individual WL and a boundary WL, (Chang, fig 5, 6, “[0065] The memory sub-system controller 115 can maintain multiple additional sub-BFEA offset tables 506, each one associated with one or more parameters… whether the data is stored in a boundary wordline or an inner wordline. [0067] The adaptive BFEA component 113 can then identify the appropriate additional sub-BFEA offset table 506 based on the sub-BFEA parameters, such as the value of a media state metric ( e.g., the number of program/erase cycles performed on the memory device), whether the data is stored in a boundary wordline or an inner wordline, the difference between the boundary wordline and the wordline storing the data, and/or the wordline group of the wordline. [0068] The adaptive BFEA component 113 can then additively apply the identified threshold voltage offset to the base voltage read level in order to perform the requested read operation.”; using the conditions of the word line to select the correct read voltage offset based on the: WL residing in a partially programmed ‘portion of the memory device”; and the location within the block; at the boundary WL both the table 504 and one or more tables 506 for data stored in a “boundary WL or an inner WL” offset can be added to arrive at the adaptive offset; Change teaches using a table 506 for inner WL only. Note: a “portion” of a memory device could be one word line).
wherein the inner WL offset values are retrieved from an inner WL offset table, and wherein the boundary WL offset values are retrieved from a boundary WL offset table. (Chang, fig 5, 6, “For example, different additional sub-BFEA offset tables 506 are used for boundary wordlines than for inner wordlines since the voltage shift and the page RBER may be more severe for data stored in the boundary wordline than for data stored in an inner wordline.”; that different tables can be generated and used as additional 506 tables depending on whether the WL is on the boundary or an “inner WL”).
Regarding claim 15, Chang teaches The system of claim 1, wherein determining whether the portion of the memory device is available for writing data comprises accessing a cursor that tracks writing progress within the portion. (Chang, fig 1, 6, “[0025] These threshold voltage shift phenomena can affect partially programmed blocks differently than they affect fully programmed blocks. [0072] The full block indicator can be stored in metadata of the physical block. For example, the full block indicator can be a binary flag, with a value of “0” to indicate that the corresponding block is partially programmed, and a value of “l” to indicate that that the corresponding block is fully programmed.”; a block can be identified (i.e. tracked) as fully programmed (i.e. closed) or partially programmed (i.e. open) Note: open and closed blocks are defined in applicant’s specification paragraph 0014).
Regarding claim 16, Chang teaches The system of claim 1, wherein the memory device comprises a three-dimensional (3D) NAND device. (Chang, fig 1, “[0039] Some examples of non-volatile memory devices (e.g., memory device 130) include a not-and (NAND) type flash memory and write-in-place memory, such as a three-dimensional cross-point (“3D cross-point”) memory device,”; the system can be a 3D NAND memory architecture).
Regarding claim 17, Chang teaches:
At least one non-transitory machine-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: (Chang, fig 8, “[0087] FIG. 8 illustrates an example machine of a computer system 800 within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, can be executed. [0097] A machine- readable medium includes any mechanism for storing information in a form readable by a machine.”; a memory device with host and sub-system processors which execute programming instructions stored in a mechanism (i.e. non-transitory)).
receiving a request to read data from a portion of a memory device; in response to receiving the request to read the data, determining whether the portion of the memory device is available for writing data; and (Chang, fig 1, 6, 8, “[0070] At operation 610, the processing logic receives a read command specifying a logical address. The processing logic can receive the read command from a host system, such as host system 120 of FIG. 1. [0072] At operation 630, responsive to determining that the physical block is partially programmed, the processing logic identifies a threshold voltage offset associated with the wordline. [0019] A partially programmed block (or a partial block) refers to a block in which not every wordline has been programmed. The most recently programmed wordline can be referred to as the boundary wordline. The wordlines following the boundary wordline are not programmed; that is, the cells connected to the wordlines following the boundary wordline are in an erase state.”; a device which first receives a read command, the device checks if the target block is partially programmed (with erased word lines, which are available for writing.)).
selectively applying boundary word line (WL) offset values to read one or more WLs of the portion of the memory device in addition to applying inner WL offset values in response to determining whether the portion of the memory device is available for writing data.3 303.Q19US1 (2024150625-US) (Chang, fig 5, 6, “[0065] The memory sub-system controller 115 can maintain multiple additional sub-BFEA offset tables 506, each one associated with one or more parameters… whether the data is stored in a boundary wordline or an inner wordline. [0067] The adaptive BFEA component 113 can then identify the appropriate additional sub-BFEA offset table 506 based on the sub-BFEA parameters, such as the value of a media state metric ( e.g., the number of program/erase cycles performed on the memory device), whether the data is stored in a boundary wordline or an inner wordline, the difference between the boundary wordline and the wordline storing the data, and/or the wordline group of the wordline. [0068] The adaptive BFEA component 113 can then additively apply the identified threshold voltage offset to the base voltage read level in order to perform the requested read operation.”; using the conditions of the word line to select the correct read voltage offset based on the: WL residing in a partially programmed ‘portion of the memory device”; and the location within the block; at the boundary WL both the table 504 and one or more tables 506 for data stored in a “boundary WL or an inner WL” offset can be added to arrive at the adaptive offset. Note: a “portion” of a memory device could be one word line).
Regarding claim 18, Chang teaches:
A method comprising: (Chang, fig 8, “[0087] FIG. 8 illustrates an example machine of a computer system 800 within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, can be executed. [0097] A machine- readable medium includes any mechanism for storing information in a form readable by a machine.”; a memory device with host and sub-system processors which execute programming instructions stored in a mechanism).
receiving a request to read data from a portion of a memory device; in response to receiving the request to read the data, determining whether the portion of the memory device is available for writing data; and (Chang, fig 1, 6, 8, “[0070] At operation 610, the processing logic receives a read command specifying a logical address. The processing logic can receive the read command from a host system, such as host system 120 of FIG. 1. [0072] At operation 630, responsive to determining that the physical block is partially programmed, the processing logic identifies a threshold voltage offset associated with the wordline. [0019] A partially programmed block (or a partial block) refers to a block in which not every wordline has been programmed. The most recently programmed wordline can be referred to as the boundary wordline. The wordlines following the boundary wordline are not programmed; that is, the cells connected to the wordlines following the boundary wordline are in an erase state.”; a device which first receives a read command, the device checks if the target block is partially programmed (with erased word lines, which are available for writing.)).
selectively applying boundary word line (WL) offset values to read one or more WLs of the portion of the memory device in addition to applying inner WL offset values in response to determining whether the portion of the memory device is available for writing data. (Chang, fig 5, 6, “[0065] The memory sub-system controller 115 can maintain multiple additional sub-BFEA offset tables 506, each one associated with one or more parameters… whether the data is stored in a boundary wordline or an inner wordline. [0067] The adaptive BFEA component 113 can then identify the appropriate additional sub-BFEA offset table 506 based on the sub-BFEA parameters, such as the value of a media state metric ( e.g., the number of program/erase cycles performed on the memory device), whether the data is stored in a boundary wordline or an inner wordline, the difference between the boundary wordline and the wordline storing the data, and/or the wordline group of the wordline. [0068] The adaptive BFEA component 113 can then additively apply the identified threshold voltage offset to the base voltage read level in order to perform the requested read operation.”; using the conditions of the word line to select the correct read voltage offset based on the: WL residing in a partially programmed ‘portion of the memory device”; and the location within the block; at the boundary WL both the table 504 and one or more tables 506 for data stored in a “boundary WL or an inner WL” offset can be added to arrive at the adaptive offset. Note: a “portion” of a memory device could be one word line).
Regarding claim 19, Chang teaches:
The method of claim 18, wherein the portion is determined to be available for writing data in response to determining that the portion comprises an open memory block, (Chang, fig 1, 6, 8, “[0070] At operation 610, the processing logic receives a read command specifying a logical address. The processing logic can receive the read command from a host system, such as host system 120 of FIG. 1. [0072] At operation 630, responsive to determining that the physical block is partially programmed, the processing logic identifies a threshold voltage offset associated with the wordline. [0019] A partially programmed block (or a partial block) refers to a block in which not every wordline has been programmed. The most recently programmed wordline can be referred to as the boundary wordline. The wordlines following the boundary wordline are not programmed; that is, the cells connected to the wordlines following the boundary wordline are in an erase state.”; a device which first receives a read command, the device checks if the target block is partially programmed (with erased word lines, which are available for writing); partially programmed blocks are considered “open” because the erased lines are open for programming, then tables 504 and/or 506 are applied based on status of the memory portion).
wherein the portion is determined to be unavailable for writing data in response to determining that the portion comprises a closed memory block. (Chang, figs 3, 4, “[0061] As illustrated by FIGS. 3 and 4, cells in a partial block experience higher voltage shift at time 0 than cells in a full block, and wordlines of a partial block experience higher page RBER than wordlines in a full block. [0064] [0064] The memory sub-system controller 115 can maintain a default BFEA offset table 504, and one or more additional sub-BFEA offset tables 506.”; that different tables can be generated based on open, closed, inner WLs, or boundary WLs for reading offset voltages).
Regarding claim 20, Chang teaches The method of claim 19, comprising: in response to determining the portion is available for writing data, applying the inner WL offset values without boundary WL offset values to read one or more WLs of the portion of the memory device; and in response to determining the portion is unavailable for writing data, applying both inner WL offset values and boundary WL offset values to read the one or more WLs of the portion of the memory device. (Chang, fig 5, 6, “[0065] The memory sub-system controller 115 can maintain multiple additional sub-BFEA offset tables 506, each one associated with one or more parameters… whether the data is stored in a boundary wordline or an inner wordline. [0067] The adaptive BFEA component 113 can then identify the appropriate additional sub-BFEA offset table 506 based on the sub-BFEA parameters, such as the value of a media state metric ( e.g., the number of program/erase cycles performed on the memory device), whether the data is stored in a boundary wordline or an inner wordline, the difference between the boundary wordline and the wordline storing the data, and/or the wordline group of the wordline. [0068] The adaptive BFEA component 113 can then additively apply the identified threshold voltage offset to the base voltage read level in order to perform the requested read operation.”; using the conditions of the word line to select the correct read voltage offset based on the: WL residing in a partially programmed ‘portion of the memory device”; and the location within the block; at the boundary WL both the table 504 and one or more tables 506 for data stored in a “boundary WL or an inner WL” offset can be added to arrive at the adaptive offset. Note: a “portion” of a memory device could be one word line).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONALD H.B. BRASWELL whose telephone number is (469)295-9119. The examiner can normally be reached on 7-5 Central Time (Dallas).
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825
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