DETAILED ACTION
This correspondence is in response to the communications received 03/09/2026. Claim 7 has been withdrawn. Claims 1-9 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-6, 8, and 9 in the reply filed on 03/09/2026 is acknowledged.
Claim 7 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 03/09/2026.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 01/14/2025 and 08/27/2025 have been considered by the examiner and made of record in the application file.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 requires “a first gate electrode region … having a largest area” on page 1, lines 34-35 and page 2, lines 1-2. This limitation is rendered indefinite by the phrase “a largest area” which implies a comparison with the size of other regions or areas, however no other areas are presented as a reference with which to make this comparison. Thus, “a largest area” does not sufficiently define the metes and bounds of claim 1 and the claim is therefore indefinite. Claims 2-9, by virtue of their dependence, inherit the deficiencies of claim 1.
Claim 1 requires “a first resistance element region … having a largest area” on page 2, lines 3-6. In addition to the indefiniteness described above, wherein a comparison is made without a clear reference, this limitation requires a second “largest area”. The first gate electrode region and the first resistance element region may not both have “a largest area”, thus claim 1 is indefinite. Claims 2-9, by virtue of their dependence, inherit the deficiencies of claim 1.
Claim 2 requires “a second gate electrode region … having a largest area” on page 2, line 35 and page 3, lines 1-3. This limitation is rendered indefinite by the phrase “a largest area” which implies a comparison with the size of other regions or areas, however no other areas are presented as a reference with which to make this comparison. Thus, “a largest area” does not sufficiently define the metes and bounds of claim 2 and the claim is therefore indefinite. Claims 3-9, by virtue of their dependence, inherit the deficiencies of claim 1.
Claim 2 requires “a second resistance element region … having a largest area” on page 3, lines 4-7. In addition to the indefiniteness described above, wherein a comparison is made without a clear reference, this limitation requires a second “largest area”. The second gate electrode region and the second resistance element region may not both have “a largest area”, thus claim 2 is indefinite. Claims 3-9, by virtue of their dependence, inherit the deficiencies of claim 1.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, a semiconductor device (1) that is a facedown mountable, chip-size-package type semiconductor device, the semiconductor device comprising:
a semiconductor layer (40) that includes a semiconductor substrate (32, see Fig. 1);
a first vertical metal-oxide semiconductor (MOS) transistor (10) an entirety of which is provided in a first region (A1) of the semiconductor layer, on a top face side of the semiconductor layer;
a second vertical MOS transistor (20) an entirety of which is provided in a second region (A2) adjacent to the first region in a plan view of the semiconductor layer (see Fig. 2); and
a metal layer (40) that is connected to and in contact with the semiconductor substrate, on a bottom face side of the semiconductor layer (see Fig. 1),
wherein the semiconductor substrate is a common drain region of the first vertical MOS transistor and the second vertical MOS transistor ("Semiconductor substrate 32 is a common drain region of first vertical MOS transistor 10 and second vertical MOS transistor 20", page 23, lines 27-28),
in the plan view, the semiconductor layer is in a square shape (see Fig. 2),
in the plan view, the first region and the second region are arranged in a first direction (see Fig. 2),
in the plan view, a border line (90) between the first region and the second region is a straight line that is orthogonal to the first direction, divides an area of the semiconductor layer in half, and passes through a center of the semiconductor layer (see Fig. 2),
in the plan view, the first region includes only one first source pad (111) and only one first gate pad (119, see Fig. 2), the one first source pad being connected to a first source electrode (11) of the first vertical MOS transistor, the one first gate pad being connected to a first gate electrode (19) of the first vertical MOS transistor (see Fig. 3),
the first vertical MOS transistor includes:
a first gate resistance element (41) that is connected to the first gate electrode (see Fig. 3);
a first gate electrode region (G1) that is a rectangular region encompassing the one first gate pad in the plan view, including neither the first source electrode nor the first gate resistance element, and having a largest area (see Fig. 3); and
a first resistance element region (R1) that is a rectangular region encompassing the first gate resistance element in the plan view, including neither the first source electrode nor the first gate electrode region, and having a largest area (see Fig. 3),
in the plan view, an entire length of an outer peripheral side among outer peripheral sides of the first gate electrode region and an entire length of an outer peripheral side among outer peripheral sides of the first resistance element region match a portion of an outer peripheral side among outer peripheral sides of the semiconductor layer, the outer peripheral side among the outer peripheral sides of the semiconductor layer being orthogonal to the border line and having a shortest distance to the one first gate pad (see Fig. 3), and
in the plan view, the outer peripheral sides of the first resistance element region include only one corner portion among four corner portions of an outer periphery of the first gate electrode region, the one corner portion having a shortest distance to the border line and a shortest distance to one of outer peripheral sides among the outer peripheral sides of the semiconductor layer, the outer peripheral sides among the outer peripheral sides of the semiconductor layer being orthogonal to the border line (see Fig. 3).
Allowable Subject Matter
Claims 1-6, 8, and 9 would be allowable if rewritten or amended to overcome the rejections under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or fairly suggest the semiconductor as recited in the claims of the instant application.
Regarding claim 1, the prior art of Fujioka et al. (US 20200395479 A1) in combination with Miyata (US 8,431,998 B2) discloses a similar semiconductor device but fails to disclose the specific claims of the instant application regarding the geometry and structure of the semiconductor layer, the first and second regions, the first gate electrode region, and the first resistance element region e.g. “in the plan view, the semiconductor layer is in a square shape, in the plan view, the first region and the second region are arranged in a first direction,
in the plan view, a border line between the first region and the second region is a straight line that is orthogonal to the first direction, divides an area of the semiconductor layer in half, and passes through a center of the semiconductor layer,
in the plan view, the first region includes only one first source pad and only one first gate pad, the one first source pad being connected to a first source electrode of the first vertical MOS transistor, the one first gate pad being connected to a first gate electrode of the first vertical MOS transistor,
the first vertical MOS transistor includes:
a first gate resistance element that is connected to the first gate electrode;
a first gate electrode region that is a rectangular region encompassing the one first gate pad in the plan view, including neither the first source electrode nor the first gate resistance element, and having a largest area; and
a first resistance element region that is a rectangular region encompassing the first gate resistance element in the plan view, including neither the first source electrode nor the first gate electrode region, and having a largest area,
in the plan view, an entire length of an outer peripheral side among outer peripheral sides of the first gate electrode region and an entire length of an outer peripheral side among outer peripheral sides of the first resistance element region match a portion of an outer peripheral side among outer peripheral sides of the semiconductor layer, the outer peripheral side among the outer peripheral sides of the semiconductor layer being orthogonal to the border line and having a shortest distance to the one first gate pad, and
in the plan view, the outer peripheral sides of the first resistance element region include only one corner portion among four corner portions of an outer periphery of the first gate electrode region, the one corner portion having a shortest distance to the border line and a shortest distance to one of outer peripheral sides among the outer peripheral sides of the semiconductor layer, the outer peripheral sides among the outer peripheral sides of the semiconductor layer being orthogonal to the border line”.
Claims 2-6, 8, and 9 would be allowable by virtue of their dependence on claim 1.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN M KUPP whose telephone number is (571)272-5608. The examiner can normally be reached Monday - Friday, 7:00 am - 4:00 pm PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893