Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Mishra (Patent Application Publication 2021/0303185) in view of Tanaka (Patent Application Publication 2008/0239811).
Claim 1. A memory system comprising: a memory device including a plurality of blocks (NVM array inducing physical erase and logic erase blocks, Mishra Fig 3, 4 [0031-0034]); and a memory controller configured to control the memory device (storage controller and block allocation manager control memory operations, Mishra Figs 6-8 [0005, 0035, 0088-0091]), wherein each of the plurality of blocks includes a plurality of sub blocks with different sizes (physical erase block may be divided into two or more sub adj blocks, Mishra Fig 3-5 [0034-0038]), wherein, in a write operation on a selected block among the plurality of blocks, in which the write operation is first to be performed, based on status information about the plurality of sub blocks included in the selected block (target storage block is selected based on tracking table status, Mishra Fig 9-10 [0083-0091].) but does not disclose the memory controller selects one of the plurality of sub blocks included in the selected block as a start sub block.
Tanaka discloses selecting a memory block based on a rewrite count, which corresponds to an erase count for the purpose of wear leveling and differences in erase counts (Tanaka Fig 5, 13 [0067-0068]).
Since Mishra and Tanaka are both from the same field of endeavor (NVM flash), the purpose disclosed by Tanaka would have been recognized in the pertinent art of Mishra.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to apply Tanaka’s erase count based selection logic when selecting the first sub-block for a write operation in Mishra’s sub block mode for the purpose of wear leveling and differences in erase counts (Tanaka Fig 5, 13 [0067-0068]).
Claim 2. The memory system of claim 1, wherein the memory controller selects the start sub block based on erase count information about the plurality of sub blocks included in the selected block (Program and erase count data in tracking table, Mishra Fig 9 [0083-0085], number of rewrites defined as a number of erases for each block, Tanaka Fig 5 [0090]).
Claim 3. The memory system of claim 2, wherein the memory controller selects a sub block, whose erase count is smallest, from among the plurality of sub blocks included in the selected block as the start sub block (searching for block having least number of rewrites, Tanaka Fig 13 [0170]. Sub-blocks are independently programmed erased and read, Mishra [0034-0038]).
Claim 4. The memory system of claim 1, wherein the memory controller selects the start sub block based on I/O pattern information about data stored in the selected block and based on block closing information about the selected block (workload type determined from write command pattern and target block selected based on a workload type, Mishra Fig 10 [0088-0091]).
Claim 5. The memory system of claim 4, wherein, when data stored in the selected block are non-burst data and a block closing for the selected block is performed in a previous round, the memory controller selects the start sub block by using a wrap-around algorithm (Random workload type and sequential workload type used to select sub-block mode or full-block, Mishra Fig 10 [0088-0091]. Buffer region preferably used cyclically to avoid data writing concentrating on a specific block, Tanaka [0184]).
Claim 6. The memory system of claim 1, wherein the memory controller selects the start sub block based on sub block size information about the plurality of sub blocks included in the selected block (sub-blocks formed by wordlines on opposite sides of a joint and tracked for sub-block operation Mishra Figs 3-5, 9 [0034-0038,0083-0085]).
Claim 7. The memory system of claim 6, wherein, when sizes of the plurality of sub blocks included in the selected block are similar to each other, the memory controller selects the start sub block by using a random algorithm (random workload type identifier from the write command and used for sub-block mode operation, Mishra Fig 10 [0088-0091]).
Claim 8. The memory system of claim 1, wherein the memory controller calculates a penalty value of the start sub block and when the penalty value is greater than a threshold value (threshold distribution condition Mishra [0039-0040]), the memory controller selects, as a new start sub block, one of remaining sub blocks among the plurality of sub blocks other than the start sub block (wear leveling activated when rewrite count reaches a predetermined ratio or when difference between most and least rewrite counts reaches a limit, Tanaka Fig 13, 16 [0161, 0170, 0218-0230]).
Claim 9. The memory system of claim 1, wherein each of the plurality of blocks includes a plurality of memory cells vertically stacked on a substrate (3D NAND memory array with vertically arranged structure, Mishra Figs 3-5 [0001-0004,0035-0038]), wherein a first sub block and a second sub block included in a first block are separated by a first sub block separation line disposed at a first height from the substrate (fabrication joint between tiers divides physical block into sub-blocks, Mishra Fig 3-5 [0035-0038]), and wherein a third sub block and a fourth sub block included in a second block are separated by a second sub block separation line disposed at a same height as the first sub block separation line (fabrication joint between tiers used to divide physical blocks in to sub-blocks, Mishra Fig 3-5 [0035-0038]).
Claim 10. The memory system of claim 9, wherein each of the first block and the second block includes a lower channel structure vertically formed on the substrate and an upper channel structure formed on the lower channel structure (two-tier memory hole architecture with a join between tiers, Mishra Fig 3-5 [0035-0038]), wherein the first sub block separation line is disposed on an interface between the lower channel structure and the upper channel structure of the first block (fabrication joint between tiers divides word lines into source-side and drain-side sub-blocks, Mishra Fig 3-5 [0035-0038]), and wherein the second sub block separation line is disposed on an interface between the lower channel structure and the upper channel structure of the second block (fabrication joint between tiers divides wordlines into source-side and drain-side sub-blocks, Mishra Fig 3-5 [0035-0038]).
Claim 11. A memory system comprising: a memory device including a plurality of blocks (NVM array including physical erase blocks, Mishra Fig 3, 5 [0031-0034]); and a memory controller configured to control the memory device (storage controller and block allocation manager control memory operation, Mishra Figs 6-8 [0005, 0088-0091]), wherein each of the plurality of blocks includes: a first sub block (first sister sub-block of a physical erase block, Mishra Figs 3, 9 [0034-0038, 0083-0085]); a second sub block disposed adjacent to the first sub block (sister sub-blocks formed on opposites sides of a fabrication joint, Mishra Fig 3-5 [0035-0038]); a third sub block disposed adjacent to the second sub block (each physical block may be divided into two or more physical sister sub-blocks, Mishra [0034-0038]), and wherein the memory controller includes: a feature table including status information about the first sub block, the second sub block and the third sub block included in a selected block among the plurality of blocks (metablock tracking table including mode, availability, write temperature, and program erase count metadata, Mishra, Fig 9 [0083-0085]); and a sub block selector configured to select one among the first sub block, the second sub block and the third sub block in which a write operation is first to be performed, based on the feature table (block allocation manager references tracking table to designate available blocks for write commands, Mishra Fig 9-10 [0083-0091]), but does not disclose the memory controller selects one of the plurality of sub blocks included in the selected block as a start sub block.
Tanaka discloses selecting a memory block based on a rewrite count, which corresponds to an erase count for the purpose of wear leveling and differences in erase counts (Tanaka Fig 5, 13 [0067-0068]).
Since Mishra and Tanaka are both from the same field of endeavor (NVM flash), the purpose disclosed by Tanaka would have been recognized in the pertinent art of Mishra.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to apply Tanaka’s erase count based selection logic when selecting the first sub-block for a write operation in Mishra’s sub block mode for the purpose of wear leveling and differences in erase counts (Tanaka Fig 5, 13 [0067-0068]).
Claim 12. The memory system of claim 11, wherein the status information includes erase count information about the first sub block, the second sub block and the third sub block included in the selected block, and wherein the sub block selector selects a sub block, whose erase count is smallest, from among the first sub block, the second sub block and the third sub block included in the selected block as the start sub block (program and erase count data in tracking table, Mishra Fig 9 [0083-0085]. Number of rewrites defines as number of erases and least rewrite count searched for wear leveling, Tanaka Fig 3, 13 [0090-0170]).
Claim 13. The memory system of claim 11, wherein the status information includes I/O pattern information about data stored in the selected block, block closing information about the selected block, and information about the start sub block, and wherein, when data stored in the selected block in a previous round are non-burst data and a block closing for the selected block is performed in the previous round, the sub block selector selects the start sub block by using a wrap-around algorithm (write workload type determined from write command pattern and used for block allocation, Mishra Fig 10 [0088-0091]. Buffer region preferably used cyclically to void data writing concentrating on a specific block, Tanka [0184]).
Claim 14. The memory system of claim 1 1, wherein the status information includes sub block size information about the first sub block, the second sub block and the third sub block, and wherein, when sizes of the first sub block, the second sub block and the third sub block are similar to each other, the sub block selector selects the start sub block by using a random algorithm (sub-blocks formed by wordlines around a joint and random workload type used for sub-block mode, Mishra Figs 3-5, 10 [0034-0038, 0088-0091]).
Claim 15. The memory system of claim 11, wherein the sub block selector re-selects the start sub block, based on penalty values of the first sub block, the second sub block and the third sub block (threshold disturb condition for sub-blocks, Mishra [0039-0040]. Wear leveling based on rewrite count imbalance between most and least rewritten blocks, Tanaka Fig 16 [0218-0230]).
Claim 16. An operating method of a memory system which includes a plurality of blocks, the method comprising: allocating a block, in which a write operation is to be performed, from among the plurality of blocks (target storage block designated to receive write commands, Mishra Fig 10 [0088-0091]); selecting sub block, in which a write operation is first to be performed, from among a plurality of sub blocks included in the allocated block, based on status information of the plurality of sub blocks (tracking table status used by block allocation manager, Mishra Fig 9 [0083-0085]); and performing a write operation sequentially from the start sub block (wordlines programmed in sequential order and write commands directed to target block, Mishra Fig 4 [0062-0063, 0088-0091]), but does not disclose the memory controller selects one of the plurality of sub blocks included in the selected block as a start sub block.
Tanaka discloses selecting a memory block based on a rewrite count, which corresponds to an erase count for the purpose of wear leveling and differences in erase counts (Tanaka Fig 5, 13 [0067-0068]).
Since Mishra and Tanaka are both from the same field of endeavor (NVM flash), the purpose disclosed by Tanaka would have been recognized in the pertinent art of Mishra.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to apply Tanaka’s erase count based selection logic when selecting the first sub-block for a write operation in Mishra’s sub block mode for the purpose of wear leveling and differences in erase counts (Tanaka Fig 5, 13 [0067-0068]).
Claim 17. The method of claim16, wherein selecting the start sub block includes: determining whether sizes of the plurality of sub blocks are similar to each other; and when the sizes of the plurality of sub blocks are similar to each other, selecting the start sub block by using a random algorithm (sub-blocks formed by wordlines around a joint and random workload type used for sub-block mode, Mishra Figs 3-5, 10 [0034-0038, 0088-0091]).
Claim 18. The method of claim 16, wherein selecting the start sub block includes: determining whether data stored in the allocated block in a previous write operation are non-burst data and whether a block closing operation on the allocated block is performed; and when the data stored in the allocated block in the previous write operation are the non- burst data and the block closing operation on the allocated block is performed, selecting the start sub block by using a wrap-around algorithm (write workload type determined from write command pattern and used for block allocation, Mishra Fig 10 [0088-0091]. Buffer region preferably used cyclically to avoid data writing concentrating on a specific block, Tanaka [0184]).
Claim 19. The method of claim 16, wherein selecting the start sub block includes: selecting a sub block, whose erase count is smallest, from among the plurality of sub blocks as the start sub block (number of rewrites defined as number or erased and searched for block having least number of rewrites, Tanaka Fig 5, 13 [0090-0170]. Sub-blocks independently programmed erased and read, Mishra [0034-0038]).
Claim 20. The method of claim 16, further comprising: calculating a penalty value of the start sub block; and when the penalty value is greater than a threshold value, selecting, as a new start sub block, one of remaining sub blocks among the plurality of sub blocks other than the start sub block (threshold disturb condition for sub-blocks, Mishra [0039-0040]. Wear leveling activated based on predetermined ratio or difference between most and least rewrite counts, Tanaka Fig 13, 16 [0161, 0170, 0218-0230]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason Lappas whose telephone number is (571) 270-1272. The examiner can normally be reached on M-F 7:30AM-5:00PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON LAPPAS/
Primary Examiner, Art Unit 2827
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