DETAILED ACTION
This non-final action is responsive to the following communications: application filed on 01/14/2025.
Claims 1-20 are pending. Claims 1, 17, and 18 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. D) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. E) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
No Priority
4. See ADS, no priority is in the record.
No Information Disclosure Statement
5. No IDS has been filed as of this Office action date. If applicable, applicant is
reminded of the duty to disclose material information under 37 C.F.R. 1 .56 (See for
example e.g. 37 C.F.R. § 1.56(c)(1) and 37 C.F.R. § 1.56(c)(3)).
Applicant is requested to check other claim, specification, disclosure informality. Requested to check language issues (e.g. antecedent issues, redundant limitation issues, grammar issues, spec congruence with con application etc.) for all claims and disclosure to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Interpretation (invoking 35 U.S.C. §112(f))
6. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are claims 1-2, 8-14, and 17-19:
For apparatus claims 1-2, 8-14: “…processing device…configured to…”
(1) “…determining a center of valley (Co V) shift … die…” (claim 1, line 5)
(2) “…generating a read offset…counts…” (claim 1, lines 6-9)
(3) “…applying the ROBP lookup table…” (claim 1, lines 10-11)
(4) “…operations…measuring read level…PEC intervals…” (claim 2, lines 1-3)
(4) “…operations…measuring valley shifts … specific read level…” (claim 8, lines 1-3)
(5) “…operations…accessing…ROBP … manufacture … testing…” (claim 9, lines 1-3)
(6) “…selecting a sacrificial block …memory…die…” (claim 9, lines 4-5)
(7) “…applying fast cycling to the sacrificial block…” (claim 9, line 6)
(8) “…measuring slow charge loss (SCL) … sacrificial block…” (claim 9, line 7)
(9) “…testing operations…determining…shift …generate…system operations…” (claim 10, lines 1-3)
(10) “…testing operations …repeating the testing probe testing…” (claim 11, lines 1-3)
(11) “…measuring threshold voltage distributions for multiple read… memory die…” (claim 11, lines 4-5)
(12) “…calculating read level off set values …distributions…” (claim 11, lines 6-7)
(13) “…testing operations…screening…individual…probe testing…” (claim 12, lines 1-3)
(14) “…identifying failing trigger rate memory dies…” (claim 12, line 4)
(15) “…applying the generated ROBP … pass screening…” (claim 12, lines 5-6)
(16) “… determining …measuring bit error counts for level 7 …” (claim 13, lines 1-2)
(17) “…updating the ROBP lookup table … measured bit error …” (claim 13, line 3)
(18) “…determining the Co-V shift…measuring a … plurality of levels…” (claim 14, lines 1-2)
(19) “…comparing … measured valley center… original read level…” (claim 14, line 3)
(20) “…updating the ROBP …original read level…” (claim 14, lines 4-5)
For method/ CRM claims 17-19: “…operations comprising…” or “…method comprising…”
(21) “…determining…center of valley…shift…memory die…” (claim 17, line 4)
(22) “…generating… read offset …program-erase count (PEC) counts…” (claim 17, lines 5-8)
(23) “…applying the ROBP lookup table … threshold voltage degradation…” (claim 17, lines 9-10)
(24) “…determining…center of valley…shift…memory die…” (claim 18, line 2)
(25) “…generating… read offset …program-erase count (PEC) count…” (claim 18, lines 3-6)
(26) “…applying the ROBP lookup table … threshold voltage degradation…” (claim 18, lines 7-8)
(27) “…measuring read level variations … PEC intervals…” (claim 19, lines 2-2)
The term "…processor…configured to…" or, “…operations comprising…” or “…method comprising…” in each of the limitations (1) through (27) above is a generic placeholder that is not preceded by a structural modifier. For instance, none of the modifiers of “…processor…configured to...” or “…operations comprising…” or “…method comprising…” or associated terms with processor/ method/ operation recites structure to perform the respective function(s).
Because the limitations above are being interpreted under 35 U.S.C. 112(f), they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. However, the specification does not appear to set forth corresponding structure(s) for the recited functions in the “…processor…configured to...” or “…operations comprising…” or “…method comprising…” limitations (1) through (27) above.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
7. The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL. — The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
8. Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1-2, 8-14, and 17-19 fail to comply with the written description requirement, because the claims recite functions in the “…processor…configured to...” or “…operations comprising…” or “…method comprising…” limitations (1) through (27) above (see Claim Construction Section in this Office action) without having adequate support for corresponding structure(s) in the specification as these claim limitations invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (see Claim Interpretation above as set forth in this Office action). As such, 1-2, 8-14, 17-19 recite functions that have no limits and covers every conceivable means for achieving the stated function in each of the limitations (1)-(27) above. That is, the Applicant fails to provide corresponding structure or acts that one of ordinary skill in the art would be able to determine its structural or functional equivalence. Without being able to determine this, how would one of ordinary skill in the art have the requisite notice that to infringe on the claim.
Disclosure Fig. 1: 117 or, Fig. 4: processing device, spec para [0030], para [0038] shows that “processor” or “processing device” type means which can be hardware, software or a combination of hardware/ software. It is not clear what “processor” or “processing device” encompasses and Fig 1 or Fig. 4 fails to show any circuitry besides showing a conceptual box. Spec fails to show any specific hardware associated with “processor”. From disclosure it is not clear if the processor is performing the operations (1)-(27). Limitations directed to functional operations which requires specific/ additional hardware details for performing the functions.
For example (not all illustrated):
(1) “…determining a center of valley (Co V) shift … die…” (claim 1, line 5) (Requires specific hardware, e.g. media operations manager circuitry details)
(2) “…generating a read offset…counts…” (claim 1, lines 6-9) (Requires specific hardware, e.g. voltage generator)
(4) “…operations…measuring read level…PEC intervals…” (claim 2, lines 1-3) (Requires specific hardware, e.g. sensing, measuring hardware)
(5) “…operations…accessing…ROBP … manufacture … testing…” (claim 9, lines 1-3) (Requires specific hardware, e.g. access mechanism)
(6) “…selecting a sacrificial block …memory…die…” (claim 9, lines 4-5) (Requires specific hardware, e.g. selector circuit, mux circuitry)
Therefore, functions in the “…processor…configured to...” or “…operations comprising…” or “…method comprising…” limitations (1) through (27) above invokes the scrutiny of interpretation under 35 U.S.C. 112(f) and requires that the Applicant affirmatively disclaim that the Applicant wishes to be limited to particular corresponding structure(s) in the written description or amend the claim to falls outside of scrutiny of interpretation under 35 U.S.C. 112(f). Accordingly, the disclosure is not commensurate with the scope of the claims.
Dependent claims inclusive of claims 1-20 are rejected under the same category.
Claim Rejections - 35 USC § 112
9. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. — The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
10. Claims 1-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Here, the claim 1-2, 8-14, and 17-19 are indefinite, because it is unclear what
corresponding structure(s) for performing the entire claimed functions in the “…processor…configured to...” or “…operations comprising…” or “…method comprising…” limitations (1) through (27) above (See Claim Interpretation section above) are as the written description fails to clearly disclose or link the corresponding structure to the entire claimed function. Each of functions in the “…processor…configured to...” or “…operations comprising…” or “…method comprising…” limitations (1) through (27) above invokes the scrutiny of interpretation under 35 U.S.C. 112(f) and requires that the Applicant affirmatively disclaim that the Applicant wishes to be limited to particular corresponding structure(s) in the written description or amend the claim to falls outside of scrutiny of interpretation under 35 U.S.C. 112(f). Disclosure Fig. 1: 117 or, Fig. 4: processing device, spec para [0030], para [0038] shows that “processor” or “processing device” type means which can be hardware, software or a combination of hardware/ software. It is not clear what “processor” or “processing device” encompasses and Fig 1 or Fig. 4 fails to show any circuitry besides showing a conceptual box. Spec fails to show any specific hardware associated with processor or, method or operation. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
All dependent claims inclusive of claims 1-20 are rejected under the same category.
The Applicant can amend:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
Or
The Applicant can affirmatively disclaim:
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01 (o) and 2181.
Claim Rejections - 35 USC § 103
11. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
12. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
13. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
14. Claim(s) 1, 8, and 13-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rayaprolu et al. (US 2022/0415412 A1), in view of Sheperek et al. (US 2022/0108758 A1).
Regarding independent claim 1, Rayaprolu teaches a system (Fig. 1: 100 computing system) comprising:
a memory device (Fig. 1: 135, 140 memory device); and
a processing device (Fig. 1: 115), operatively coupled to the memory device (Fig. 1: 135, 140), configured to perform operations comprising:
determining a center of valley (Co-V) shift for an individual memory die (Fig. 2-Fig. 5 in context of para [0050]-para [0051]: “valley shift” is determined for dies using method described);
generating a read offset (para [0024]: “valley metric”) by program-erase count (ROBP) (para [0021]: “data state metric” BEC, RBER) lookup table (Fig. 6: 610, 620) individually associated with the individual memory die (Fig. 6: 610 die 1…die N) based on the determined Co-V shift (para [0050]-para [0051]: “valley shift” and associated method is used),
the ROBP lookup table including read level offset values for different word line groups (Fig. 6: 620 WLG) program-erase count (PEC) counts (para [0020], para [0021]: “data state metric” BEC, RBER); and
applying the ROBP lookup table to adjust read levels for the individual memory die (para [0049]: “…read threshold voltages are adjusted to compensate for the shift in program distribution…”) during memory operations to compensate for threshold voltage degradation (para [0049], para [0054]).
Rayaprolu is silent with respect to using PEC for read level adjustment.
Sheperek teaches generating read offset by using program-erase count (ROBP) individually associated with the individual memory die (Fig. 8: Tables combined) individually associated with the individual memory die (para [0061], para [0062], para [0066]: PEC is used for read level adjustment and being used in Fig. 8 Tables. Fig. 6: 610, 620 use of PEC).
Rayaprolu and Sheperek are in the same field of endeavor of NAND flash memory sense operation improvement and they are in analogous field of art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to use the teachings of Sheperek into the teachings of Rayaprolu such that PEC can be employed in order to reduce “… extra burden on resources needed to perform…scans can be reduced…” (Sheperek para [0058]) and reduce “…trigger margin loss…” related to read errors (Sheperek para [0067]); and reduce noise/ disturbance during reading.
Regarding claim 8, Rayaprolu, and Sheperek teach the system of claim 1. Rayaprolu teaches the operations comprising: measuring valley shifts between adjacent threshold voltage distributions of a specific read level (See Rayaprolu para [0050]-para [0053]).
Regarding claim 13, Rayaprolu, and Sheperek teach the system of claim 1. Rayaprolu teaches wherein determining the Co V shift comprises: measuring bit error counts for level 7 of a plurality of levels; and
updating the ROBP lookup table based on the measured bit error counts for level 7 (Rayaprolu Fig. 2-Fig. 4 in context of para [0051], para [0052]: scan valley 7 and measure RBER or BEC).
Regarding claim 14, Rayaprolu, and Sheperek teach the system of claim 1. Rayaprolu teaches wherein determining the Co V shift comprises: measuring a valley center for level 7 of a plurality of levels (Rayaprolu Fig. 2-Fig. 4 in context of para [0052]: scan only valley 1 and / or valley 7);
comparing the measured valley center to an original read level; and updating the ROBP lookup table based on a shift between the measured valley center at the plurality of levels and the original read level (Rayaprolu Fig. 2-Fig. 4 disclosure in context of para [0052], para [0051]: valley shift determination method).
Regarding claim 15, Rayaprolu, and Sheperek teach the system of claim 1. Rayaprolu teaches wherein the memory device comprises a tri-level cell (TLC) NAND flash memory device (Rayaprolu para [0018]: TLC).
Regarding claim 16, Rayaprolu, and Sheperek teach the system of claim 1. Rayaprolu teaches wherein the memory device comprises a three-dimensional (3D) NAND device (Rayaprolu para [0033]).
Regarding independent claim 17, Rayaprolu, and Sheperek teach at least one non-transitory machine-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations (see Rayaprolu para [0079], para [0080]: “machine-readable storage medium”) comprising:
determining a center of valley (Co V) shift for an individual memory die;
generating a read offset by program-erase count (ROBP) lookup table individually associated with the individual memory die based on the determined CoV shift, the ROBP lookup table including read level offset values for different word line groups and program-erase count (PEC) counts; and
applying the ROBP lookup table to adjust read levels for the individual memory die during memory operations to compensate for threshold voltage degradation.
(This claim is drafted as in CRM method format, substantially identical to the functionality recited in claim 1, and is therefore rejected for the same reasons as claim 1).
Regarding independent claim 18, Rayaprolu, and Sheperek teach a method comprising:
determining a center of valley (Co V) shift for an individual memory die;
generating a read offset by program-erase count (ROBP) lookup table individually associated with the individual memory die based on the determined Co V shift, the ROBP lookup table including read level offset values for different word line groups and program-erase count (PEC) counts; and
applying the ROBP lookup table to adjust read levels for the individual memory die during memory operations to compensate for threshold voltage degradation.
(This claim is drafted as in method format, substantially identical to the functionality recited in claim 1, and is therefore rejected for the same reasons as claim 1).
15. Claim(s) 2-7, and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rayaprolu et al. (US 2022/0415412 A1) and Sheperek et al. (US 2022/0108758 A1), in further view of Liu et al. (US 2023/0195354 A1).
Regarding claim 2, Rayaprolu and Sheperek teach the system of claim 1. Rayaprolu and Sheperek are silent with respect to measuring read level variations during system background scan operations at predetermined PEC intervals.
Liu teaches operations comprising: measuring read level variations during system background scan operations at predetermined PEC intervals (Liu Fig. 2: 220 in context of para [0020], para [0046]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to use the teachings of Liu into the teachings of Rayaprolu and Sheperek such that system background scan can be employed to check and track PEC in order to improve operation speed.
Regarding claim 3, Rayaprolu, Sheperek, and Liu teach the operations of claim 2. Liu teaches wherein the predetermined PEC intervals comprise at least one of 3,000 cycles, 7,000 cycles, or 10,000 cycles (Liu Fig. 2: 220 in context of para [0020], para [0046]: see 7000 cycles).
Regarding claim 4, Rayaprolu, and Sheperek teach the system of claim 1. Rayaprolu teaches wherein the ROBP lookup table comprises read level offset values for at least fifteen- word line groups (Rayaprolu Fig. 6: 620: disclosed N is any number and encompasses the limitation). Rayaprolu does not explicitly teach that ROBP lookup table comprises read level offset values for at least fifteen- word line groups
Liu teaches in Fig. 2: 210 than number of scan groups can be 16.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to use the teachings of Liu into the teachings of Rayaprolu and Sheperek such that at least 15-word line group can be employed to check and track PEC in order to improve operation speed and reduce group scan error.
Regarding claim 5, Rayaprolu, Sheperek, and Liu teach the system of claim 4. Rayaprolu teaches the ROBP lookup table comprises read level offset values for at least seven read levels (See Rayaprolu para [0018], Fig. 2: read levels shown).
Regarding claim 6, Rayaprolu, Sheperek, and Liu teach the system of claim 5. Liu teaches wherein the ROBP lookup table comprises read level offset values for at least four different PEC ranges (Liu Fig. 2: 210, 220, 240).
Regarding claim 7, Rayaprolu, Sheperek, and Liu teach the system of claim 6. Liu teaches wherein the PEC ranges comprise 0-999 cycles, 1000-2999 cycles, 3000-6999 cycles, and 7000+ cycles (Liu Fig. 2: 210, 220, 240).
Regarding claim 19, Rayaprolu, Sheperek, and Liu teach the method of claim 18, comprising:
measuring read level variations during system background scan operations at predetermined PEC intervals.
(This claim is drafted as in method format, substantially identical to the functionality recited in claim 2, and is therefore rejected for the same reasons as claim 1).
Regarding claim 20, Rayaprolu, Sheperek, and Liu teach the method of claim 19, wherein the predetermined PEC intervals comprise at least one of 3,000 cycles, 7,000 cycles, or 10,000 cycles. (This claim is drafted as in method format, substantially identical to the functionality recited in claim 3, and is therefore rejected for the same reasons as claim 3).
16. Claim(s) 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rayaprolu et al. (US 2022/0415412 A1) and Sheperek et al. (US 2022/0108758 A1), in further view of Lang (US 2025/0201326 A1).
Regarding claim 9, Rayaprolu and Sheperek teach the system of claim 1. Rayaprolu and Sheperek are silent with respect to remaining provisions of this claims which pertains to testing during manufacturing to generate lookup tables.
Lang teaches operations comprising:
accessing the ROBP table generated during manufacture of the individual memory die (para [0057]: see manufacturing, probe),
the ROBP table generated during manufacture by performing testing operations comprising: selecting a sacrificial block during wafer-level probe testing of the individual memory die; (para [00576]-para [0062]: use of sacrificial block and probe test)
applying fast cycling to the sacrificial block; and (para [00576]-para [0062]: test condition)
measuring slow charge loss (SCL) behavior of the sacrificial block. (para [0057]-para [0062]: charge loss test).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to use the teachings of Lang into the teachings of Rayaprolu and Sheperek such that die-level BFEA component can be employed to populate reliability parameters in order to reduce cost.
Regarding claim 10, Rayaprolu, Sheperek, and Lang teach the system of claim 9. Lang teaches the testing operations comprising:
determining the Co-V shift based on the measured SCL behavior to generate the ROBP lookup table before the individual memory die is used in system operations (para [0062]-para [0063]).
Regarding claim 11, Rayaprolu, Sheperek, and Lang teach the system of claim 10. Lang teaches the testing operations comprising: repeating the testing operations for each memory die during the wafer-level probe testing; operations (para [0062]-para [0063]),
measuring threshold voltage distributions for multiple read levels in the sacrificial block of each respective memory die; and operations (para [0062]-para [0063]).
calculating read level offset values based on the measured threshold voltage distributions. operations (para [0062]-para [0063]).
No art rejection provided for claims 9-14. See 112b rejections
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure:
Rayaprolu (US 2022/0155956 A1): Fig. 1-Fig. 15 disclosure applicable for all claims. KRISHNAN et al. (US 2014/0281128 A1): KRISHNAN teaches a method (Fig. 6D: 600 processes of reading stored data that minimizes read error) comprising:
generating a first set of read data associated with a memory component, the first set of read data comprising a first sequence of bit values (Fig. 6D: 628: first read amongst plural reads on target memory location using first “voltage threshold” and populating first “data pattern”, see Fig. 6D: 628 in context of para [0027], lines 1-6, para [0041], lines 14-19. See TABLE1 in para [0025]: multiple read samples).
It is suggested that applicant consider all prior arts made of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached 7:00 am-4:00 pm.
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825
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