DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 3-9, 11, 12, and 14-20 have been amended.
Claims 2 and 13 have been /cancelled.
Claims 1, 3-12, and 14-20 have been examined.
The specification and claim objections in the previous Office Action have been addressed and are withdrawn, except as otherwise indicated below.
The § 101 rejections in the previous Office Action have been addressed and are withdrawn.
Specification
The disclosure is objected to because of the following informalities.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Appropriate correction is required. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 11 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 11 recites, “the other memory.” There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this limitation is interpreted as, “the memory.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 7, 9, 11, 12, 18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Publication No. 2013/0159668 by Muff et al. (hereinafter referred to as “Muff”).
Regarding claims 1 and 12, taking claim 1 as representative, Muff discloses:
a computing device comprising: one or more processors comprising processing circuitry; and memory storing instructions configured to, when executed by the one or more processors, cause the computing device to: receive and decode an instruction stream comprising instructions to obtain pieces of instruction-information respectively corresponding to the instructions (Muff discloses, at Figure 5 and related description, a processor that receives an instruction stream from an iCache and decodes the instruction stream. As disclosed at Figure 7 and related description, the instruction stream includes instructions, i.e., opcodes, and instruction information, e.g., operands.);
sequentially match portions of the instructions to portions of a predefined instruction pattern based on the pieces of instruction information of the portions of the instructions (Muff discloses, at Figure 6 and related description, analyzing groups of instructions, and their operands, to determine whether they match a scalar instruction pattern that can be vectorized.); and
based on results of the matching, translate the instructions of the instruction stream to a second instruction stream, the translating comprising translating at least some of the instructions of the instruction stream to vector instructions in a vector-specific instruction set by replacing instructions …with functionally equivalent second instructions of a second-specific ISA (Muff discloses, at Figure 5 and related description, generating functionally equivalent vector instructions of a vector instruction set architecture by replacing scalar instructions. As disclosed at ¶ [0055], this is to support new instructions that were unsupported in previous versions of the ISA.).
Regarding claims 7 and 18, taking claim 7 as representative, Muff discloses the elements of claim 1, as discussed above. Muff also discloses:
the instructions are further configured to cause the computing device to: when there is an instruction to be translated to a second instruction using a register value for the instruction stream, translate the instruction stream into the second instruction stream using the register value obtained through an access device (Muff discloses, at Figure 5 and related description, generating functionally equivalent vector instructions, which discloses using the registers. As disclosed at ¶ [0067], accessing registers is done via read ports, which discloses an access device.).
Regarding claims 9, Muff discloses the elements of claim 1, as discussed above. Muff also discloses:
a buffer memory (Muff discloses, at Figure 5 and related description, an instruction buffer.); and
a decoder, wherein the decoder is configured to: receive the instruction stream from the buffer memory or receive the second instruction stream from a module that performs the translating, and wherein the instructions are further configured to cause the computing device to: receive a second instruction stream comprising second instructions from the buffer memory, and transfer the translated second instruction stream to the decoder (Muff discloses, at Figure 5 and related description, a decoder that receives instructions from the instruction buffer or translated instructions, which discloses multiple instruction streams and transfers.).
Regarding claims 11 and 20 taking claim 11 as representative, Muff discloses the elements of claim 1, as discussed above. Muff also discloses:
a memory device comprising the other memory, wherein the memory device is configured to perform at least one of: storing a new instruction pattern; determining whether the instruction stream is translatable into the second instruction stream based on the new instruction pattern; or transferring the new instruction pattern to a module that performs the translating (Muff discloses, at Figure 5 and related description, predecode logic that stores instructions, which discloses being configured to store a new scalar instruction pattern.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Muff in view of US Publication No. 2008/0141012 by Yehia et al. (hereinafter referred to as “Yehia”).
Regarding claims 4 and 15, taking claim 4 as representative, Muff discloses the elements of claim 1, as discussed above. Muff does not explicitly disclose the instruction pattern comprises at least one of: a first instruction pattern comprising a backward branch instruction; or a second instruction pattern comprising a forward branch instruction and a backward unconditional jump instruction.
However, in the same field of endeavor (e.g., instruction translation) Yehia discloses”
an instruction pattern having a backward branch instruction (Yehia discloses, at Figure 11, a scalar loop that ends in a backward branch.)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Muff to include the backward branch disclosed by Yehia because loops are useful code structures to efficiently execute repetitive operations and are commonly implemented with backward branches or jumps.
Claims 5 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Muff in view of US Publication No. 2023/0205535 by Al Sheikh et al. (hereinafter referred to as “Al Sheikh”).
Regarding claims 5 and 16, taking claim 5 as representative, Muff discloses the elements of claim 1, as discussed above. Muff does not explicitly disclose determine whether the instructions in the instruction stream are translatable into a vector stream includes: determining, based on source register information and destination register information of the instructions comprised in the instruction stream, the presence or absence of a register association between the instructions; when there is an absence of an association between the instructions, determine that the instruction stream is not translatable into a second instruction stream; and when there is a presence of an association between the instructions, determine that the instruction stream is translatable into a second instruction stream.
However, in the same field of endeavor (e.g., instruction optimization) Al Sheikh discloses:
determine, based on source register information and destination register information of the instructions comprised in the instruction stream, the presence or absence of a register association between the instructions (Al Sheikh discloses, at Figure 9A and related description, analyzing source and destination registers to determine dependency.);
when there is an absence of an association between the instructions, determine that the instruction stream cannot be optimized; and when there is a presence of an association between the instructions, determine that the instruction stream can be optimized (Al Sheikh discloses, at Figure 9A and related description, that dependencies must be resolved to continue execution. If a dependency cannot be resolved in time, the code cannot be optimized.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Muff to include the operand association determination disclosed by Al Sheikh because operand dependencies are common and must be properly addressed to prevent execution delays.
Claims 8 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Muff in view of US Publication No. 2014/0052962 by Hertzberg et al. (hereinafter referred to as “Hertzberg”).
Regarding claims 8 and 19, taking claim 8 as representative, Muff discloses the elements of claim 1, as discussed above. Muff also discloses:
…the instruction stream is flushed from a buffer memory and the second instruction stream is inputted to the buffer memory (Muff discloses, at Figure 5 and related description, selecting between the instruction buffer, i.e., the instruction stream, and predecode logic, i.e., the vector instruction stream, and removing the instructions from the instruction buffer.).
Muff does not explicitly disclose a cache memory device configured to store a record of translating the instruction stream into the second instruction stream, and the aforementioned flush and input are in the presence of the record stored in the cache memory device.
However, in the same field of endeavor (e.g., instruction translation) Hertzberg discloses:
a translation trace cache that stores translations (Hertzberg discloses, at Figure 1 and related description, a translation trace cache that stores translations, which discloses a record of translating and using the record to select instructions.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Muff to include the translation trace cache disclosed by Hertzberg in order to improve performance by facilitating efficient reuse of translations.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Muff in view of US Publication No. 2019/0102197 by Kumar et al. (hereinafter referred to as “Kumar”).
Regarding claims 10, Muff discloses the elements of claim 1, as discussed above. Muff does not explicitly disclose the instruction stream comprises a predefined number of instructions.
However, in the same field of endeavor (e.g., execution optimization) Kumar discloses:
a predefined window size (Kumar discloses, at ¶ [0046], a predefined window size.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Muff to include a predefined window size, as disclosed by Hertzberg, in order to improve performance by facilitating efficient search.
Allowable Subject Matter
Claims 3, 6, 14, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
On page 7 of the response filed June 22, 2026 (“response”), the Applicant argues, “Claims 1 and 12 recite decoding instructions and translating instructions. The human mind is incapable of performing such operations, in particular binary instructions, as recited in claim 12. In addition, the claims are directed to a technical problem and incorporate a technical solution, namely, improving the utilization of processing resources by enabling the use of second instructions (e.g., vector instructions, but not only). In Enfish, LLC v. Microsoft Corp. (2016), the Federal Circuit held that software patents directed to a specific improvement in computer functionality are patent-eligible. The ruling in Enfish held that software is not inherently abstract and, if it improves computer performance, it is patentable.”
These remarks have been fully considered and, in light of the claim amendments presented in the response, are deemed persuasive. Accordingly, the § 101 rejections are withdrawn.
On pages 7-8 of the response the Applicant argues, “The rejection of claims 3-11 and 14-20 is further traversed because a prima facie rejection has not been presented by the Office. As noted in The 2019 Revised Patent Subject Matter Eligibility Guidance (2019 PEG) published on January 7, 2019 (84 Fed. Reg. 50): [T]he initial burden is on the examiner to explain why a claim or claims are ineligible for patenting clearly and specifically, so that the applicant has sufficient notice and is able to effectively respond. Examiners should review the record as a whole and make subject matter eligibility decisions on a claim-by-claim basis in accordance with the broadest reasonable interpretation of the claims. Because a prima facie rejection of the dependent claims has not been provided, the rejection of the dependent claims is further in error.”
Though fully considered, the Examiner respectfully disagrees. However, as the rejection is withdrawn based on the previous argument, this argument is moot.
On page 9 of the response the Applicant argues, “Muff has no teaching or suggestion of sequentially matching portions of the instructions to portions of a predefined instruction pattern based on the pieces of instruction-information of the portions of the instructions, or translating to a second ISA based on the matching. Muff uses predecode logic 218. Muff's only description of such predecoding is "analyz[ing] instructions in the instruction buffer to identify a plurality of scalar instructions indicating independent operations that are summed at the end by a last, dependent scalar add instruction" (par. 0064). Muff appears to teach using circuitry configured to algorithmically analyze instructions. Nowhere does Muff teach matching portions of instructions to portions of a pattern stored in memory, nor does Muff require such a technique since it is presumably able to achieve its purpose without such a feature. The rejection of claim 2 (now cancelled) cites Muff's determining whether instructions match a scalar instruction pattern. However, this is a determination about the instructions themselves and does involve determining if portions of the instructions match portions of a pattern stored in memory. Determining that instructions form a particular pattern (as per the rejection of claim 2) is not the same as determining that the instructions match a pattern in memory, where the pattern is an existing object against which a match is determined. Finally, claim 1 recites decoding the instruction stream to obtain pieces of instruction- information comprising information about the instructions extracted by decoding the instructions, which are used for pattern matching. Muff's predecoding simply analyzes instructions and replaces them. There is no separate step of obtaining pieces of information about the instructions -- the instructions themselves are used to determine whether to perform a scalar-to- vector instruction replacement.”
Though fully considered, the Examiner respectfully disagrees. Muff discloses analyzing scalar instructions to determine if they match a pattern that can be vectorized. See, e.g., ¶ [0064]. See also ¶ [0057]. This implicitly discloses sequentially matching portions of the instructions, e.g., the opcodes. If the instructions match a certain pattern, then they can be vectorized. Otherwise, they cannot.
Determining if the instruction stream includes instructions that can be vectorized discloses obtaining pieces of information about the instructions, including, e.g., opcodes and operand identifiers. For example, ¶ [0057] discusses a string of independent instructions followed by a dependent instruction. This discloses obtaining both opcodes and operand identifiers, which are pieces of instruction information. Accordingly, the Applicant’s arguments are deemed unpersuasive.
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/
Primary Examiner, Art Unit 2183
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