DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 25 September 2026 has been entered.
CLAIM INTERPRETATION
Claims in this application are not interpreted under 35 U.S.C. §112(f).
Claim Objections
Claims 3-5, 11-13, 18, 20 and 22 are objected to because of the following informalities:
Claims 3, 11 and 18 recite “second commands”, however, there were never any commands previously introduced as “first commands”. Therefore, the use of “second” is inappropriate unless other commands are labeled as “first” commands or else a different differentiator should be used.
Claims 4 and 12 are objected to for failing to cure the deficiencies of a base claim from which they depend.
Commands 5, 13 and 20 recite, pause or pausing “commands assigned to the second queue”, which as best understood by the Examiner in light of the specification, should be amended to recite pause or pausing “issuance of commands assigned to the second queue”.
Claim 22 recites, “commands from the second queue or third queue have not issued”, which as best understood by the Examiner in light of the specification, should be amended to recite “commands from the second queue or third queue have not been issued”.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 7-9, 14-16 and 21-22 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 6, 8, 13 and 15 of U.S. Patent No. US 12,229,452 B2 (‘452). Although the claims at issue are not identical, they are not patentably distinct from each other because Claims 1, 6, 8, 13 and 15 of ‘452 contains every element of claims 1, 7-9, 14-16 and 21-22 of the instant application and as such anticipates claims 1, 7-9, 14-16 and 21-22 of the instant application.
"A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896,225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berq, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). " ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Instant Application
‘452
1. A memory system, comprising: one or more memory devices; and a processing device coupled with the one or more memory devices and configured to cause the memory system to:
assign respective sets of commands to a first queue, a second queue, or a third queue of a memory device of the one or more memory devices, wherein the first queue, the second queue, and the third queue are associated with a first priority, a second priority, and a third priority, respectively, the first priority greater than the second priority and the second priority greater than the third priority;
issue one or more commands of a respective set of commands assigned to the second queue or the third queue based at least in part on a counter that indicates issuance of a threshold number of commands from the first queue without issuance of commands from the second queue or the third queue.
8. A memory system, comprising: one or more memory devices; and processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
assign a first set of commands to a first queue of a memory die of a memory sub-system, wherein the first queue is associated with a first priority level, wherein the memory die includes a second queue associated with a second priority level and a third queue associated with a third priority level, wherein the third priority level is greater than the second priority level, and the first priority level is greater than the third priority level, the second queue comprising a second set of commands assigned to the second queue;
instantiate a timer to determine an amount of time that a second command of the second set of commands from the second queue has not issued; increment a counter each time that a command of the first set of commands issues without the second command of the second set of commands issuing from the second queue; determine that a threshold number of the first set of commands of the first queue have issued without the second command of the second set of commands issuing from the second queue and that a threshold amount of time is satisfied by the timer, wherein the threshold number is selected based at least in part on both previous system performance and current system performance; determine that the third queue is empty;
issue, based at least in part on determining that the threshold number of the first set of commands of the first queue have issued without the second command of the second set of commands issuing from the second queue or determining that the third queue is empty, one or more commands of the second set of commands, wherein the one or more commands of the second set of commands comprises the second command; and issue, after issuing the one or more commands of the second set of commands, a third command of the first set of commands.
7. The memory system of claim 1, wherein the memory device is associated with a respective sub-system of the memory system.
8…a first queue of a memory die of a memory sub-system…
8. The memory system of claim 1, wherein a command included in a respective set of commands assigned to the first queue comprises a host read command.
13. The memory system of claim 8, wherein the first set of commands comprise host read commands, and wherein the second set of commands comprise at least one of a host write command, a read command, a write command, or an erase command.
9. A method by a memory system, comprising:
assigning respective sets of commands to a first queue, a second queue, or a third queue of a memory die, wherein the first queue, the second queue, and the third queue are associated with a first priority, a second priority, and a third priority, respectively, the first priority greater than the second priority and the second priority greater than the third priority; and
issuing one or more commands of a respective set of commands assigned to the second queue or the third queue based at least in part on a counter that indicates issuance of a threshold number of commands from the first queue without issuance of commands from the second queue or the third queue.
1. A method by a memory system, comprising:
assigning a first set of commands to a first queue of a memory die of a memory sub-system, wherein the first queue is associated with a first priority level, wherein the memory die includes a second queue associated with a second priority level and a third queue associated with a third priority level, wherein the third priority level is greater than the second priority level, and the first priority level is greater than the third priority level, the second queue comprising a second set of commands assigned to the second queue; instantiating a timer to determine an amount of time that a second command of the second set of commands from the second queue has not issued; incrementing a counter each time that a command of the first set of commands issues without the second command of the second set of commands issuing from the second queue; determining that a threshold number of the first set of commands of the first queue have issued without the second command of the second set of commands issuing from the second queue and that a threshold amount of time is satisfied by the timer, wherein the threshold number is selected based at least in part on both previous system performance and current system performance; determining that the third queue is empty;
issuing, based at least in part on determining that the threshold number of the first set of commands of the first queue have issued without the second command of the second set of commands issuing from the second queue or determining that the third queue is empty, one or more commands of the second set of commands, wherein the one or more commands of the second set of commands comprises the second command; and issuing, after issuing the one or more commands of the second set of commands, a third command of the first set of commands.
14. The method of claim 9, wherein the memory die is associated with a respective sub-system of the memory system.
1…a memory die of a memory sub-system…
15. The method of claim 9, wherein a command included in a respective set of commands assigned to the first queue comprises a host read command.
6. The method of claim 1, wherein the first set of commands comprise host read commands, and wherein the second set of commands comprise at least one of a host write command, a read command, a write command, or an erase command.
16. A non-transitory computer-readable medium storing code, the code comprising instructions executable by a memory system to:
assign respective sets of commands to a first queue, a second queue, or a third queue of a memory die, wherein the first queue, the second queue, and the third queue are associated with a first priority, a second priority, and a third priority, respectively, the first priority greater than the second priority and the second priority greater than the third priority; and
issue one or more commands of a respective set of commands assigned to the second queue or the third queue based at least in part on a counter that indicates issuance of a threshold number of commands from the first queue without issuance of commands from the second queue or the third queue.
15. A non-transitory computer-readable storage medium comprising instructions that, when executed by processing circuitry of an electronic device, cause the electronic device to:
assign a first set of commands to a first queue of a memory die of a memory sub-system, wherein the first queue is associated with a first priority level, wherein the memory die includes a second queue associated with a second priority level and a third queue associated with a third priority level, wherein the third priority level is greater than the second priority level, and the first priority level is greater than the third priority level, the second queue comprising a second set of commands assigned to the second queue; instantiate a timer to determine an amount of time that a second command of the second set of commands from the second queue has not issued; increment a counter each time that a command of the first set of commands issues without the second command of the second set of commands issuing from the second queue; determine that a threshold number of the first set of commands of the first queue have issued without the second command of the second set of commands issuing from the second queue and that a threshold amount of time is satisfied by the timer, wherein the threshold number is selected based at least in part on both previous system performance and current system performance; determine that the third queue is empty;
issue, based at least in part on determining that the threshold number of the first set of commands of the first queue have issued without the second command of the second set of commands issuing from the second queue or determining that the third queue is empty, one or more commands of the second set of commands, wherein the one or more commands of the second set of commands comprises the second command; and issue, after issuing the one or more commands of the second set of commands, a third command of the first set of commands.
21. The memory system of claim 1, wherein the processing device is further configured to cause the memory system to: issue a plurality of commands of the respective set of commands assigned to the second queue or the third queue before issuing a next command of a respective set of commands assigned to the first queue.
15…issue, based at least in part on determining that the threshold number of the first set of commands of the first queue have issued without the second command of the second set of commands issuing from the second queue or determining that the third queue is empty, one or more commands of the second set of commands, wherein the one or more commands of the second set of commands comprises the second command; and issue, after issuing the one or more commands of the second set of commands, a third command of the first set of commands.
22. The memory system of claim 1, wherein the threshold number of commands from the first queue is based at least in part on a threshold amount of time during which commands from the second queue or the third queue have not issued.
15…instantiate a timer to determine an amount of time that a second command of the second set of commands from the second queue has not issued… issue, based at least in part on determining that the threshold number of the first set of commands of the first queue have issued without the second command of the second set of commands issuing from the second queue or determining that the third queue is empty, one or more commands of the second set of commands, wherein the one or more commands of the second set of commands comprises the second command; and issue, after issuing the one or more commands of the second set of commands, a third command of the first set of commands.
Claims 2-5, 10-13 and 17-18 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 8, and 15 of ‘452 in view of US Patent Application Publication US 2018/0217951 A1 (Benisty).
Instant Application
Benisty
2. The memory system of claim 1 (is made obvious by claim 8 of ‘452 as seen in the rejection above)
wherein the processing device is further configured to cause the memory system to: issue, prior to issuing the one or more commands of the respective set of commands assigned to the second queue or the third queue, one or more commands of a respective set of commands assigned to the first queue.
Benisty teaches the conventional consequence of priority-based queue arbitration – higher priority commands are issued if the higher priority command queues are not empty, otherwise lower priority commands are issued. Furthermore, Benisty teaches that the issuing of commands from a lower priority queue may be paused/stopped/interrupted if a command becomes queued in a higher-priority queue, after which, issuance of commands from the lower-priority queue may be resumed according to the conventional priority order (high to low) depending on which queues are not empty [0081] [0084] [0105] [0112].
3. The memory system of claim 1 (is made obvious by claim 8 of ‘452 as seen in the rejection above)
wherein the processing device is further configured to cause the memory system to: assign a command to the first queue or the second queue; and pause issuance of one or more second commands of the respective set of commands assigned to the third queue based at least in part on assigning the command to the first queue or the second queue.
Benisty teaches the conventional consequence of priority-based queue arbitration – higher priority commands are issued if the higher priority command queues are not empty, otherwise lower priority commands are issued. Furthermore, Benisty teaches that the issuing of commands from a lower priority queue may be paused/stopped/interrupted if a command becomes queued in a higher-priority queue, after which, issuance of commands from the lower-priority queue may be resumed according to the conventional priority order (high to low) depending on which queues are not empty [0081] [0084] [0105] [0112].
4. The memory system of claim 3, wherein the processing device is further configured to cause the memory system to: issue the command assigned to the first queue or the second queue; and resume issuance of the one or more second commands of the respective set of commands assigned to the third queue based at least in part on issuing the command assigned to the first queue or the second queue.
Benisty teaches the conventional consequence of priority-based queue arbitration – higher priority commands are issued if the higher priority command queues are not empty, otherwise lower priority commands are issued. Furthermore, Benisty teaches that the issuing of commands from a lower priority queue may be paused/stopped/interrupted if a command becomes queued in a higher-priority queue, after which, issuance of commands from the lower-priority queue may be resumed according to the conventional priority order (high to low) depending on which queues are not empty [0081] [0084] [0105] [0112].
5. The memory system of claim 1 (is made obvious by claim 8 of ‘452 as seen in the rejection above)
wherein the processing device is further configured to cause the memory system to: pause commands assigned to the second queue.
Benisty teaches the conventional consequence of priority-based queue arbitration – higher priority commands are issued if the higher priority command queues are not empty, otherwise lower priority commands are issued. Furthermore, Benisty teaches that the issuing of commands from a lower priority queue may be paused/stopped/interrupted if a command becomes queued in a higher-priority queue, after which, issuance of commands from the lower-priority queue may be resumed according to the conventional priority order (high to low) depending on which queues are not empty [0081] [0084] [0105] [0112].
10. The method of claim 9 (is made obvious by claim 1 of ‘452 as seen in the rejection above)
further comprising: issuing, prior to issuing the one or more commands of the respective set of commands assigned to the second queue or the third queue, one or more commands of a respective set of commands assigned to the first queue.
Benisty teaches the conventional consequence of priority-based queue arbitration – higher priority commands are issued if the higher priority command queues are not empty, otherwise lower priority commands are issued. Furthermore, Benisty teaches that the issuing of commands from a lower priority queue may be paused/stopped/interrupted if a command becomes queued in a higher-priority queue, after which, issuance of commands from the lower-priority queue may be resumed according to the conventional priority order (high to low) depending on which queues are not empty [0081] [0084] [0105] [0112].
11. The method of claim 9 (is made obvious by claim 1 of ‘452 as seen in the rejection above)
further comprising: assigning a command to the first queue or the second queue; and pausing issuance of one or more second commands of the respective set of commands assigned to the third queue based at least in part on assigning the command to the first queue or the second queue.
Benisty teaches the conventional consequence of priority-based queue arbitration – higher priority commands are issued if the higher priority command queues are not empty, otherwise lower priority commands are issued. Furthermore, Benisty teaches that the issuing of commands from a lower priority queue may be paused/stopped/interrupted if a command becomes queued in a higher-priority queue, after which, issuance of commands from the lower-priority queue may be resumed according to the conventional priority order (high to low) depending on which queues are not empty [0081] [0084] [0105] [0112].
13. The method of claim 9 (is made obvious by claim 1 of ‘452 as seen in the rejection above)
further comprising: pausing commands assigned to the second queue.
Benisty teaches the conventional consequence of priority-based queue arbitration – higher priority commands are issued if the higher priority command queues are not empty, otherwise lower priority commands are issued. Furthermore, Benisty teaches that the issuing of commands from a lower priority queue may be paused/stopped/interrupted if a command becomes queued in a higher-priority queue, after which, issuance of commands from the lower-priority queue may be resumed according to the conventional priority order (high to low) depending on which queues are not empty [0081] [0084] [0105] [0112].
17. The non-transitory computer-readable medium of claim 16 (is made obvious by claim 15 of ‘452 as seen in the rejection above)
wherein the instructions are further executable by the memory system to: issue, prior to issuing the one or more commands of the respective set of commands assigned to the second queue or the third queue, one or more commands of a respective set of commands assigned to the first queue.
Benisty teaches the conventional consequence of priority-based queue arbitration – higher priority commands are issued if the higher priority command queues are not empty, otherwise lower priority commands are issued. Furthermore, Benisty teaches that the issuing of commands from a lower priority queue may be paused/stopped/interrupted if a command becomes queued in a higher-priority queue, after which, issuance of commands from the lower-priority queue may be resumed according to the conventional priority order (high to low) depending on which queues are not empty [0081] [0084] [0105] [0112].
18. The non-transitory computer-readable medium of claim 16 (is made obvious by claim 15 of ‘452 as seen in the rejection above)
wherein the instructions are further executable by the memory system to: assign a command to the first queue or the second queue; and pause issuance of one or more second commands of the respective set of commands assigned to the third queue based at least in part on assigning the command to the first queue or the second queue.
Benisty teaches the conventional consequence of priority-based queue arbitration – higher priority commands are issued if the higher priority command queues are not empty, otherwise lower priority commands are issued. Furthermore, Benisty teaches that the issuing of commands from a lower priority queue may be paused/stopped/interrupted if a command becomes queued in a higher-priority queue, after which, issuance of commands from the lower-priority queue may be resumed according to the conventional priority order (high to low) depending on which queues are not empty [0081] [0084] [0105] [0112].
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the issuance of commands from the three queues with respective high, middle, and low priorities as taught by ‘452 to include the issuance in conventional priority order (high, middle, low) such that the commands are issued from the commands from the lower priority queues when the higher priority queues are empty, and to pause issuance of commands from the lower priority queues when the higher priority queues become no longer empty as taught by Benisty.
One of ordinary skill in the art would have been motivated to make this modification because a person of ordinary skill in the art would have appreciated that it would allow higher priority commands to receive preferential treatment (being issued before lower priority commands) associated with their higher priority status rather than waiting for continued issuance of commands from a lower-priority queue as taught by the interruption method and of the lower priority queues and arbitration method between higher and lower-priority queues of Benisty [0081] [0084] [0105] [0112].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5, 7-10, 13-17 and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. US 2021/0279001 A1 (Kanno) in view of US Patent Application Publication No. US 2002/0138670 A1 (Johnson).
Regarding claim 1 and analogous claims 9 and 16:
Kanno discloses,
a memory system (SSD (3) [Fig. 1])
comprising: one or more memory devices (NAND flash memory (5), including a plurality of memory die (i.e., 1-32) [Figs. 1-2])
and a processing device (CPU (12))
coupled with the one or more memory devices (CPU (12) is coupled to NAND flash memory (5) including the plurality of die (i.e., 1-32) through the NAND I/F (13), it controls the operation of the memory by loading and executing a control program stored in the flash memory (5) or a ROM, loaded to SRAM (16), and may implement the scheduler (21) [0061])
and configured to cause the memory system to: assign respective sets of commands to a first queue, a second queue, or a third queue of a memory device of the one or more memory devices (by disclosing the controller (4) inputting commands to different queues (i.e., any of queues 0-7) for a NAND flash memory die according to a classification method, for example, different namespaces may be associated with each queue, and [Fig. 4] [0091] [0102])
wherein the first queue, the second queue, and the third queue are associated with a first priority, a second priority, and a third priority, respectively, the first priority greater than the second priority, and the second priority greater than the third priority (by disclosing that the queues can function according to 8-level priority queueing, where all commands are issued from the highest priority queue until it is empty and then commands are issued from the next lowest priority command and so on and so forth. The priority order can be based on the queue number, such that queues with lower numbers are higher priority (i.e., queue #0 has higher priority than queue #1, queue #1 has higher priority than queue #2, and so on and so forth) [0115] [0168-0170])
and issue one or more commands of a respective set of commands assigned to the second queue or the third queue based at least in part on issuance of a number of commands from the first queue without issuance of commands from the second queue or the third queue (by disclosing that all commands would issue from the highest priority queue (queue #0), until it is empty (i.e., a number of commands from the first queue would issue without issuance of commands from the second queue), before any commands are issued from the next highest priority queue (queue #1) [0115]) [0169-0170]).
Kanno does not explicitly disclose, but Johnson teaches:
and issue one or more commands of a respective set of commands assigned to the lower priority queue (i.e., the second queue or the third queue as taught by Kanno) based at least in part on a counter that indicates issuance of a threshold number of commands from the first queue without issuance of commands from a lower priority queue (i.e., the second queue or the third queue as taught by Kanno) (by teaching that a starvation counter may provide a count of the number of high/priority requests that are issued while deferred low priority I/O requests are pending in the low priority I/O queue [0020]. In this way, if the starvation counter reaches a predetermined maximum value (i.e., threshold), a predetermined number of requests can be processed from the low priority I/O queue to prevent starvation of the low priority I/O requests, and then the starvation counter can be reset [0020] [0025]. As seen in [Fig. 4], the starvation counter only counts the number of high-priority requests that have been issued without a command issuing from the lower-priority queue, as any time a low-priority request is issued the starvation counter is reset (160) (168) [Fig. 4] [0020-0026]. It is contemplated that there may be more than two priority levels [0034]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the issuance of commands from the priority queues that issue commands from the highest priority queue (i.e., queue #0) until it is empty before issuing commands from the next highest priority queue (i.e., queue #1) as taught by Kanno to include a starvation counter that counts the number of highest priority commands that have issued (i.e., such as from queue #0 as taught by Kanno) without issuing a deferred lower priority commands queue in a lower priority queue (i.e., such as queue #1 or #2 as taught by Kanno), and then if that count reaches a threshold, issuing a predetermined number of commands from the lower priority queue (i.e., such as queue #1 or #2 as taught by Kanno) as taught by Johnson.
One of ordinary skill in the art would have been motivated to make this modification they would have identified that if commands continuously arrived at queue #0 of Kanno, commands in lower priority queues such as queue #1 or queue #2 of Kanno would be indefinitely postponed. Johnson identifies this starvation problem in priority-based I/O scheduling and teaches a known solution: count higher priority issuances while lower-priority requests remained deferred and upon reaching a predetermined threshold, issue the lower-priority requests. A person of ordinary skill in the art therefore had reason to incorporate Johnson’s starvation counter into Kanno to preserve priority preference while ensuring that lower priority commands are not queued indefinitely because the starvation counter can prevent starvation of the lower priority I/O requests if there is a stream of numerous high priority I/O requests to ensure that they are not prevented from processing for an extended period of time, which can improve performance as taught by Johnson in [0020] [0025].
Regarding claim 2 and analogous claims 10 and 17:
The memory system of claim 1 is made obvious by Kanno in view of Johnson (Kanno-Johnson).
Kanno-Johnson further make obvious:
wherein the processing device is further configured to cause the memory system to: issue, prior to issuing the one or more commands of the respective set of commands assigned to the second queue or the third queue, one or more commands of a respective set of commands assigned to the first queue (through the analysis performed for claim 1).
Regarding claim 5 and analogous claims 13 and 20:
The memory system of claim 1 is made obvious by Kanno-Johnson.
Kanno does not explicitly disclose, but Johnson teaches:
wherein, the processing device is further configured to cause the memory system to: pause commands assigned to the second queue (by teaching that only a predetermined number of commands (168) will be issued from the deferred low priority I/O requests in the low priority queue, and then commands will resume being issued from the high priority queue after the starvation counter is reset (i.e., the high priority commands will again issue without low priority commands issuing (i.e., pausing commands assigned to the second queue)) [0025]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the issuance of commands from the priority queues that issue commands from the highest priority queue (i.e., queue #0) until it is empty before issuing commands from the lower priority queues (i.e., queues #1 or #2) as taught by Kanno to include a starvation counter that counts the number of highest priority commands that have issued (i.e., such as from queue #0 as taught by Kanno) without issuing a deferred lower priority commands queue in a lower priority queue (i.e., such as queue #1 or #2 as taught by Kanno), and then if that count reaches a threshold, issuing a predetermined number of commands from the lower priority queue (i.e., such as queue #1 or #2 as taught by Kanno) as taught by Johnson.
One of ordinary skill in the art would have been motivated to make this modification because it can prevent starvation of the lower priority I/O requests if there is a stream of numerous high priority I/O requests as taught by Johnson in [0020].
Regarding claim 7 and analogous claim 14:
The memory system of claim 1 is made obvious by Kanno-Johnson.
Kanno further discloses:
wherein the memory device is associated with a respective sub-system of the memory system (by teaching that the NAND flash memory die (as seen in [Fig. 4]) associated with the plurality of queues (queues #1-#7) may be one of a plurality of memory dies in the memory system, as seen in [Figs. 1-3], which each have their own associated queues and scheduler (a respective sub-system) as seen in [Fig. 4] [0043] [0089-0091]).
Regarding claim 8 and analogous claim 15:
The memory system of claim 1 is made obvious by Kanno-Johnson.
Kanno further discloses:
wherein a command included in a respective set of commands assigned to the first queue is a host read command (by disclosing that each of the commands (erase, program, and read) can be placed in a certain queue of the eight queues for the memory die. The command, for example, may be a read command from the host (host read command) that is placed in queue #0 (first queue) [0091-0094]).
Regarding claim 21:
The memory system of claim 1 is made obvious by Kanno-Johnson.
Kanno does not explicitly disclose, but Johnson teaches
wherein, the processing device is further configured to issue a plurality of commands of the respective set of commands assigned to the second queue or the third queue before issuing a next command of a respective set of commands assigned to the first queue (by disclosing that a predetermined number of commands (168) (i.e., a plurality) will be issued from the deferred low priority I/O requests in the low priority queue when the starvation counter threshold is reached, and then commands will resume being issued from the high priority queue after the starvation counter is reset (i.e., the high priority commands will again issue without low priority commands issuing (i.e., pausing commands assigned to the second queue)) [0025]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the issuance of commands from the priority queues that issue commands from the highest priority queue (i.e., queue #0) until it is empty before issuing commands from the lower priority queues (i.e., queues #1 or #2) as taught by Kanno to include a starvation counter that counts the number of highest priority commands that have issued (i.e., such as from queue #0 as taught by Kanno) without issuing a deferred lower priority commands queue in a lower priority queue (i.e., such as queue #1 or #2 as taught by Kanno), and then if that count reaches a threshold, issuing a predetermined number of commands from the lower priority queue (i.e., such as queue #1 or #2 as taught by Kanno), before resuming execution of commands from the higher-priority queue (i.e., such as queue #1 as taught by Kanno) as taught by Johnson.
One of ordinary skill in the art would have been motivated to make this modification because it can prevent starvation of the lower priority I/O requests if there is a stream of numerous high priority I/O requests as taught by Johnson in [0020].
Claims 3-4, 11-12 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kanno-Johnson in further view of US Patent Application Publication No. US 2018/0217951 A1 (Benisty).
Regarding claim 3 and analogous claims 11 and 18:
The memory system of claim 1 is made obvious by Kanno-Johnson.
Kanno further discloses:
the respective set of commands assigned to the third queue (by disclosing the controller (4) inputting commands to different queues (i.e., any of queues 0-7) for a NAND flash memory die according to a classification method, for example, different namespaces may be associated with each queue [Fig. 4] [0091] [0102]. The queues can function according to 8-level priority queueing, where all commands are issued from the highest priority queue until it is empty and then commands are issued from the next lowest priority command and so on and so forth. The priority order can be based on the queue number, such that queues with lower numbers are higher priority (i.e., queue #0 has higher priority than queue #1, queue #1 has higher priority than queue #2, and so on and so forth) [0115] [0168-0170]).
Kanno does not explicitly disclose, but Benisty teaches:
wherein the processing device is further configured to cause the memory system to: assign a command to the first queue or the second queue; and pause issuance of one or more second commands of the respective set of commands assigned to the third queue based at least in part on assigning the command to the first queue or the second queue (by teaching that selection of commands for issuance from the lower priority queues may be interrupted (paused/stopped [0081]) in response to determining that one or more commands are available from one or more higher priority submissions queues, such that the commands from the higher priority queues may be selected for issuance [0084] [0105] [0112]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the issuance and execution of commands from a lower priority queue (such as queue #3, as taught by Kanno) to be paused when a new higher priority command is queued (such as queue in #1 or #2 as taught by Kanno) so that the higher priority command from the higher priority queue may be issued as taught by Benisty.
One of ordinary skill in the art would have been motivated to make this modification because a person of ordinary skill in the art would have appreciated that it would allow higher priority commands to receive preferential treatment (being issued before lower priority commands) associated with their higher priority status rather than waiting for continued issuance of commands from a lower-priority queue as taught by the interruption method of the lower priority queues of Benisty [0081] [0084] [0105] [0112].
Regarding claim 4 and analogous claims 12:
The memory system of claim 3 is made obvious by Kanno-Johnson in further view of Benisty in further view of Mustafa.
Kanno does not explicitly disclose, but Benisty teaches:
wherein the processing device is further configured to cause the memory system to: issue the command assigned to the first queue or the second queue; and resume issuance of the one or more second commands of the respective set of commands assigned to the third queue based at least in part on issuing the command assigned to the first queue or the second queue (by teaching that selection of commands for issuance from the low priority queues may continue while the high and medium priority queues are empty, otherwise, selection of commands for issuance can switch to the higher priority queues (i.e., and therefore pause issuance of commands from the low priority queues), however, upon the higher priority queues being empty again, commands can resume being issued from the lower priority queues again [0081] [0084] [0105] [0112]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the issuance and execution of commands from a lower priority queue (such as queue #2, as taught by Kanno) to be interrupted so that a command from a higher priority queue may be issued and executed if the higher priority queues are no longer empty as taught by Benisty, but then to resume issuance and execution of commands from the lower priority queue again (such as queue #2 as taught by Kanno) if the higher priority queues are again empty as taught by Benisty.
One of ordinary skill in the art would have been motivated to make this modification because a person of ordinary skill in the art would have appreciated that it would allow higher priority commands to receive preferential treatment (being issued before lower priority commands) associated with their higher priority status rather than waiting for continued issuance of commands from a lower-priority queue as taught by the interruption method and of the lower priority queues and arbitration method between higher and lower-priority queues of Benisty [0081] [0084] [0105] [0112].
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Kanno-Johnson in further view of US Patent No. US 5,809,278 A (Watanabe).
Regarding claim 22:
The memory system of claim 1 is made obvious by Kanno-Johnson.
Kanno does not explicitly disclose, but Johnson teaches:
wherein the threshold number of commands from the first queue is based at least in part on a threshold amount of commands that have issued from the first queue during which commands from the second queue or the third queue have not issued (through the analysis performed for claim 1).
Kanno-Johnson does not explicitly disclose, but Watanabe teaches:
That the threshold may be based at least in part on a threshold amount of time during which commands from the lower priority queues (i.e., second queue or third queue as taught by Kanno) have not issued (by teaching instead of using a counter that counts the number of high priority requests that have issued without a lower-priority request issuing, an alternative manner of determining whether a lower priority request is starved by the issuance of higher-priority requests and should be prioritized for issuance is by using a frequency divided clock to count the elapsed time, and using a waiting time threshold (interpreted in line with Applicant’s specification as representing a “threshold number of commands” – “In some examples, the threshold number provided by the counter may refer to a measure of time in which the commands have issued from the high priority queue without a command issuing from the low priority queue” [0062]) as the trigger for issuing the low-priority request that has been starved [Col 15: line 45 – Co. 16: line 42]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the starvation counter counting the number of high priority requests that have issued without a lower priority request issuing as taught by Kanno-Johnson to be substituted for a counter that tracks the elapsed time that high priority requests have been issuing without a lower priority request issuing as taught by Watanabe because it would have only required the simple substitution of one known element for another to obtain predictable results. In this case, Kanno-Johnson teaches the memory system with queues with different priority levels, issuing commands from the higher-priority queue, tracking the number of that have issued without a command issuing from the lower-priority queues with a counter, and then switching to issuing commands from the lower-priority queues when the counter reaches a threshold, which is only different from the claimed invention because it teaches counting a threshold number of commands issued from the higher priority commands as an absolute number of commands rather than a period of time. However, Watanabe teaches that a period of time may be counted while higher priority commands issue and lower-priority commands are waiting instead of an absolute number of commands that have issued from the higher priority commands while the lower-priority commands are waiting. Accordingly, one of ordinary skill in the art could have substituted the counting of commands for the counting of time and the results would have been predictable: the issuance of commands from the lower-priority queue would not be indefinitely starved by issuance of commands from the higher priority queue as they could be selected for issuance after the threshold period of waiting time was reached.
Response to Amendments/Arguments
New claim objections have been made to claims 3-5, 11-13, 18, 20 and 22.
A double patenting rejection has been made to the pending claims.
In response to the amendments to the claims, the previous 35 USC §112(b) rejection has been withdrawn.
In response to the amendments to the claims, the previous 35 USC §112(a) rejection has been withdrawn.
Applicant’s arguments in the Remarks dated 25 September 2026 (Rem) have been fully considered but are not persuasive.
Applicant argues that Kanno is fundamentally a weight-based scheduler and not a priority-queue system and therefore is not modifiable by Benisty with priority-based scheduling [Rem, pg. 9, ¶2 – pg. 10, ¶2 and pg. 10, last ¶]. However, Applicant’s characterization is not persuasive because in the embodiment which the Examiner relied upon, Kanno expressly recognizes an alternative mode that functions as 8-level priority-queueing that makes the weights irrelevant because they are set to 0, and sets priority based on queue #, and therefore Applicant’s assertion that Kanno “avoids any use of queue priority” is contradicted by Kanno itself [0115] [0168-0170].
Applicant argues that Kanno does not disclose the three queues having three respective priorities, each greater than the next, respectively. However, the Examiner respectfully disagrees as Kanno teaches an 8-level priority queuing technique where all weights are 0, in which case, according to [0115], the priority of each queue depends on its queue #, such that queue #0 would have the highest priority, queue #1 the next highest, and so on and so forth [0115] [0168-0170].
Applicant argues that Kanno’s priority embodiment only exhausts one queue and then proceeds to the next and not pausing lower-priority issuance when higher priority commands arrive in a higher priority queue. However, this is the deficiency for which the Benisty reference was relied upon, as Benisty teaches stopping/pausing issuance from a lower-priority queue when a command arrives in a higher-priority queue [0081] [0084] [0112]. Accordingly, Applicant’s argument against Kanno individually is not persuasive where the rejection is based upon a combination of references.
Applicant argues that Benisty would render Kanno inoperable for its intended purpose by replacing Kanno’s flexible weight-based workload-responsive scheduling with Benisty’s strict priority framework. However, this is not the proposed modification, as the Examiner modified Kanno’s 8-level priority queuing framework disclosed in [0168-0170] and not the flexible weight-based workload-responsive scheduling discussed in other embodiments. Furthermore, Benisty merely supplies dynamic re-arbitration or pre-emption of a lower-priority command to pause issuance of commands from the lower priority queue and instead issue commands from the higher priority queue when a higher-priority command becomes newly available in the higher-priority queue as taught by Benisty in [0081] [0084] [0112]. Accordingly, in the combination, the underlying framework of the 8-level priority queueing taught by Kanno remains intact, with the additional benefit of the added functionality of Benisty of pausing issuance of lower-priority commands when higher-priority commands are queued to provide priority to the higher-priority commands rather than waiting for continued issuance of lower priority commands as would be a benefit recognizable by one of ordinary skill in the art. Therefore, Applicant’s argument is not persuasive.
Applicant argues that Johnson belongs to “a fundamentally different context” and is only relevant to two queues with high and low priorities, respectively. The Examiner respectfully disagrees. Johnson is directed to managing scheduling/ arbitration between queues with different priority levels, and starvation of low-priority requests by the continued arrival of high-priority requests, which is relevant to Kanno’s 8-level priority queuing as one of ordinary skill in the art would recognize that if queue #0 never became empty, execution would never move on to the other lower-priority queues and those queues would have execution/issuance of their commands delayed indefinitely. Furthermore, Johnson contemplates the use of more than two priority levels in [0034]. Accordingly, one of ordinary skill in the art would recognize the usefulness and benefit of applying Johnson’s starvation counter to the issuance of commands from queue #0 of Kanno to then trigger the execution/issuance of a predetermined number of commands from lower-priority queues if the counter reaches a threshold as taught by Johson. Therefore, Applicant’s argument is not persuasive.
Applicant argues that combining Johnson’s counter with Benisty and Kanno results in an internally inconsistent modification. However, the argument improperly incorporates Benisty’s entire strict-priority embodiment. Instead, Benisty is relied upon narrowly and generally for the arrival of higher-priority commands into a high priority queue pausing issuance of lower-priority commands from a lower-priority queue, and the resumption of issuance of commands from a lower-priority queue upon the higher-priority queue becoming empty to reflect the preference for issuance/execution of commands from the higher priority queue and to prevent higher priority command issuance having to wait for issuance of lower-priority commands. These narrower and general rules are complimentary to Johnson’s starvation counter because they apply under different conditions and in different contexts. According to the teachings of Benisty and Kanno, higher priority commands generally preempt issuance of lower priority commands, such that lower priority commands are generally only issued when there is an absence of higher priority commands. However, upon issuance of commands from the higher-priority command causing the starvation counter to reach the starvation threshold, Johnson teaches to temporarily service lower-priority commands to prevent them from being starved indefinitely. Accordingly, Applicant’s argument that these references result in an internally inconsistent modification is not persuasive.
Finally, the Examiner notes that claim 1 and the other independent claims are rejected with Kanno-Johnson and therefore Applicant’s arguments which only regard the combination of Kanno, Benisty, and Johnson are not persuasive.
Claim 21 has been rejected with Kanno-Johnson according to the analysis performed above and accordingly, Applicant’s argument that it is not rendered obvious by the prior art is not persuasive.
Claim 22 has been rejected with Kanno-Johnson in further view of Watanabe and accordingly, Applicant’s arguments are moot.
As applicant’s arguments were not persuasive, the claims are not indicated as allowable.
Conclusion
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/CURTIS JAMES KORTMAN/Primary Examiner, Art Unit 2139
