DETAILED ACTION
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/14/2025 was considered by the examiner.
Claim Objections
Claim 3 is objected to because of the following informalities:
Please amend claim 3 as follows: “… wherein a second DC cut filter…”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2021/0302510 (Yonetani).
Regarding claim 1, Yonetani teaches a magnetic sensor circuit (magnetic sensor device 1 of Fig. 22), comprising:
a Hall element, through which a drive current flows by using a drive circuit, and which outputs a Hall voltage and a first offset voltage (Hall element 21 receives a drive current Ibias from a constant supply circuit 50 and outputs a measured magnetic field Vout, and it is known by one of ordinary skill in the art that a Hall sensor also comprises an offset voltage which is removed by spinning; see [0003]-[0004], [0031], [0033]; see Fig. 2);
a spinning circuit, based on a clock signal, changing a polarity that causes the drive current to flow, setting the Hall voltage as a DC component, setting the first offset voltage as an AC component, and outputting the first offset voltage (switch circuit 22 spins the current according to a spinning method based on a clock input signal CPsp, wherein the DC response of the Hall voltage and AC component of the offset voltage is a known response of the spinning method; see Figs. 2-3; see [0033]-[0034], [0096]-[0104]);
a modulation circuit, based on the clock signal, setting the Hall voltage as an AC component in a differential voltage output from the spinning circuit, and setting the first offset voltage as a DC component (modulator circuit 3 comprises a modulator/demodulator circuit with mixer 10 modulated based on clock signal CPch0 which one of ordinary skill in the art would understand the mixer 10 performs the functional limitations as claimed; see Figs. 4-5 and 21; see [0042]-[0047]);
a first DC cut filter, in a differential voltage output from the modulation circuit, allowing the Hall voltage as the AC component to pass through and cutting off the first offset voltage as the DC component, and setting, to a predetermined common-phase voltage, a common-phase voltage from the modulation circuit (a high pass filter may be placed before and after the amplifier, wherein the high-pass filter placed before the amplifier is equivalent to the claimed “first DC cut filter” which eliminates the DC offset of the Hall element 21; see [0084]);
an amplifier circuit, in a differential voltage output from the first DC cut filter, amplifying a voltage in which a second offset as a DC component is added to the Hall voltage of the AC component (an amplifier 11 receives a signal from the high-pass filter; and amplifies a signal with a gain A; see Figs. 4 and 21; see [0046]);
a demodulation circuit, in a differential voltage output from the amplifier circuit, demodulating and setting the Hall voltage as the AC component as a DC component, and demodulating the second offset voltage of the DC component as an AC component (modulator circuit 3 comprises a modulator/demodulator circuit with mixer 12 modulated based on clock signal CPch0 which one of ordinary skill in the art would understand the mixer 12 performs the functional limitations as claimed; see Figs. 4-5 and 21; see [0042]-[0047]); and
a low pass filter, in a differential voltage output from the demodulation circuit, allowing the Hall voltage as the DC component to pass through and cutting off the second offset voltage as the AC component (a low-pass filter circuit 13 receives the differential output from mixer 12 which allows the voltage signal Vout corresponding to the measured magnetic field applied to the Hall element 21; see Figs. 4 and 21; see [0045]).
Regarding claim 2, Yonetani teaches wherein the drive circuit is a constant current source using a current mirror circuit (the drive circuit 50 generates a constant current I using current mirror circuits 51, 52; see [0031], [0101]).
Regarding claim 3. The magnetic sensor circuit as claimed in claim 1, wherein the second DC cut filter is connected between the amplifier circuit and the demodulation circuit (a high pass filter may be placed before and after the amplifier, wherein the high-pass filter placed after the amplifier is equivalent to the claimed “second DC cut filter” which eliminates the DC offset of the amplifier 11; see [0084]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892
US 2016/0363638 discloses placing a high pass filter 110 following the modulation circuit 404 and before amplifier 108 as recited in claim 1 See Fig. 11 and [0065]) and a filter 406 following the modulating switches 404 and before amplifying to remove offset (see Fig. 11; see [0214]-[0216].
US 2011/0298453 shows in Fig. 7 wherein a constant-current driver circuit 34 employs a current mirror.
US 2009/0108839 shows in Fig. 2 wherein a Hall sensor is driven by current mirror 116.
US 2009/0160535 teaches wherein a current mirror is provides a more constant bias current over temperatures. See Fig. 3, [0022].
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN LEE YENINAS whose telephone number is (571)270-0372. The examiner can normally be reached M - F 10 - 6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Judy Nguyen can be reached at (571) 272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN L YENINAS/Primary Examiner, Art Unit 2858
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