DETAILED ACTION
This action is responsive to the response filed 14 Jan 2025 and the Information Disclosure Statement filed 14 Jan 2025. Claims 1-20 are pending. Claims 1, 9 and 15 are independent.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 14 Jan 2025is acknowledged. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless —
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 2, 4, 8, 9, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by In, et al, U.S. Patent Application Publication 2024/0069773 (“In”).
Regarding claim 1, In teaches:
A method comprising: detecting an event occurring on a solid state drive, (In, fig 1, “[0031] FIG. 1 shows an exemplary block diagram 100 of a storage device 102 which communicates with a host device 104 (also “host”). [0065] At 604, the controller may determine that data stored on a first block satisfies a threshold data-error condition, wherein the data comprises invalid data and valid data.”; a memory device that can detect events regarding memory status).
wherein the event includes at least one of: a program error on a physical block of a first virtual block, a read error on the physical block, or a power cycle of the solid state drive; (In, fig 1, 5, 6, “[0031] Here, the first block may be one of one or more open blocks in the storage device used to perform I/0 operations. As illustrated in FIG. 5, the stored data may have errors, rendering one or more pages as invalid.”; a device detecting a writing error from stored data).
programming user data stored in the first virtual block onto a second virtual block based on detecting the event; (In, fig 5, 6, “[0053] A controller (e.g., controller 326 of FIG. 3) may determine the first block 500 has a high BER. For example, the controller may determine that a threshold BER condition has been met. The determination may trigger the controller to perform a relocation process. [0054] The FTL may then write the valid data 508 from the first block 500 to the second block 550 and write any additional data 512 from host write commands to the second block 550.”; a system detects errors and transfers data to a second physical block FTL (flash translation layer)).
including the first virtual block in a pool of virtual blocks scheduled for erase operations; (In, fig 5, 6, “[0055] In certain aspects, once the FTL closes the first block 500, FTL may accept host writes. Then regular garbage collection flow can pick any source block to reclaim free space or to refresh a block.”; a first block with detected events has been designated as a ‘garbage’ block and ready for further processing).
determining whether the first virtual block is in an open state; and (In, fig 5, 6, “[0052] FIG. 5 is a block diagram illustrating an example of open-block relocation. [0055] In this example, the FTL may distinguish between a partially closed block and a fully closed block because a partially closed block may have different RMAP locations.”; the first block is determined to be open, it can have “dummy data” written to a sub-block 510 of fig 5, it can be partially closed or fully closed).
when the first virtual block is in the open state: programming dummy data on the first virtual block prior to performing an erase operation on the virtual block, or performing a flash write operation on the first virtual block prior to performing the erase operation on the virtual block. (In, fig 5, 6, “[0054] With the aggregate of invalid data 506, valid data 508, and dummy data 510 occupying the first eight pages of the first block 500, the FTL may close the first block, then open a second block 550 [0057] In a first example, the FTL may write dummy data 510 up to a partial close block boundary defined by a particular data length to protect previously stored data in the first block 500 and ensure generation of an error code and/or parity for any partially written data.”; the first block, at initial programming, is determined to have 3 open pages, designated by 510 of fig 5; and these 3 pages are written with dummy data).
Regarding claim 2, In teaches The method of claim 1, comprising: performing the erase operation on the virtual block after programming the dummy data or performing the flash write operation. (In, fig 5, 6, “[0072] At 616, the controller may erase the first block in response to the relocation of the valid data. That is, once the valid data has been relocated to the second block, the first block may be erased as part of a garbage collection process.”; the erasure in step 616 occurs after the dummy data 510 has been written to the subblock).
Regarding claim 4, In teaches The method of claim 1, comprising: programming the dummy data on unprogrammed wordlines of the physical block. (In, fig 5, 6, “[0054] Because there is a three open-page gap between the second boundary 504 and the fifth page, the flash translation layer (FTL) may write dummy data 510 into the three open-page gap. With the aggregate of invalid data 506, valid data 508, and dummy data 510 occupying the first eight pages of the first block 500, the FTL may close the first block, then open a second block 550”; that the physical word lines beneath the written data can be written on unprogrammed WLs; in this case 3 WLs of dummy data are written).
Regarding claim 8, In teaches The method of claim 1, comprising: determining that the virtual block is not in the open state; and performing the erase operation on the virtual block without programming the dummy data or without performing the flash write operation. (In, fig 5, 6, “[0024] In some examples, the block may be completely closed ( e.g., no new data may be written to the block), or the block may be partially closed ( e.g., new data may be written to pages that proceed from the partial close block boundary, whereas pages prior to the boundary are closed). In such an example where the block is only partially closed, the host may continue to write data to the open portions of the block.”; a block can be either open or closed; that closed blocks have no pages for new data; that blocks with filled data can proceed to erasure without writing dummy data).
Regarding claim 9, In teaches:
A system comprising: a controller to: (In, fig 1, “[0031] FIG. 1 shows an exemplary block diagram 100 of a storage device 102 which communicates with a host device 104 (also “host”). [0065] At 604, the controller may determine that data stored on a first block satisfies a threshold data-error condition, wherein the data comprises invalid data and valid data.”; a memory device that can detect events regarding memory status).
detect an event associated with a virtual block, wherein the event includes at least one of: a program error on a physical block of the virtual block, a read error on the physical block, or a power cycle of a storage device that includes the virtual block; (In, fig 1, 5, 6, “[0031] Here, the first block may be one of one or more open blocks in the storage device used to perform I/0 operations. As illustrated in FIG. 5, the stored data may have errors, rendering one or more pages as invalid.”; a device detecting a writing error from stored data).
determine whether the virtual block is in an open state; (In, fig 5, 6, “[0052] FIG. 5 is a block diagram illustrating an example of open-block relocation. [0055] In this example, the FTL may distinguish between a partially closed block and a fully closed block because a partially closed block may have different RMAP locations.”; the first block is determined to be open, it can have “dummy data” written to a sub-block 510 of fig 5, it can be partially closed or fully closed).
program data on the virtual block, prior to performing an erase operation on the virtual block, when the virtual block is in the open state; and (In, fig 5, 6, “[0054] With the aggregate of invalid data 506, valid data 508, and dummy data 510 occupying the first eight pages of the first block 500, the FTL may close the first block, then open a second block 550 [0057] In a first example, the FTL may write dummy data 510 up to a partial close block boundary defined by a particular data length to protect previously stored data in the first block 500 and ensure generation of an error code and/or parity for any partially written data. [0072] At 616, the controller may erase the first block in response to the relocation of the valid data.”; the first block, at initial programming, is determined to have 3 open pages, designated by 510 of fig 5; and these 3 pages are written with dummy data prior to an erase operation).
perform the erase operation on the virtual block, without programming the data on the virtual block, when the virtual block is not in the open state. (In, fig 5, 6, “[0024] In some examples, the block may be completely closed ( e.g., no new data may be written to the block), or the block may be partially closed ( e.g., new data may be written to pages that proceed from the partial close block boundary, whereas pages prior to the boundary are closed). In such an example where the block is only partially closed, the host may continue to write data to the open portions of the block. [0072] At 616, the controller may erase the first block in response to the relocation of the valid data.”; a block can be either open or closed; that closed blocks have no pages for new data; that blocks with filled data can proceed to erasure without writing dummy data prior to an erase operation).
Regarding claim 15, In teaches:
A non-transitory computer-readable medium storing a set of instructions, the set of instructions comprising: one or more instructions that, when executed by one or more processors of a controller, cause the controller to: detect an event associated with a first virtual block, (In, fig 1, “[0031] FIG. 1 shows an exemplary block diagram 100 of a storage device 102 which communicates with a host device 104 (also “host”). [0065] At 604, the controller may determine that data stored on a first block satisfies a threshold data-error condition, wherein the data comprises invalid data and valid data.”; a memory device that can detect events regarding memory status).
wherein the event includes at least one of: a program error on a physical block of the first virtual block, a read error on the physical block, or a power cycle of a storage device that includes the first virtual block; (In, fig 1, 5, 6, “[0031] Here, the first block may be one of one or more open blocks in the storage device used to perform I/0 operations. As illustrated in FIG. 5, the stored data may have errors, rendering one or more pages as invalid.”; a device detecting a writing error from stored data).
program user data stored in the first virtual block onto a second virtual block based on detecting the event; and (In, fig 5, 6, “[0053] A controller (e.g., controller 326 of FIG. 3) may determine the first block 500 has a high BER. For example, the controller may determine that a threshold BER condition has been met. The determination may trigger the controller to perform a relocation process. [0054] The FTL may then write the valid data 508 from the first block 500 to the second block 550 and write any additional data 512 from host write commands to the second block 550.”; a system detects errors and transfers data to a second physical block FTL (flash translation layer)).
program data on the first virtual block, prior to performing an erase operation on the first virtual block, when the first virtual block is in an open state. (In, fig 5, 6, “[0052] FIG. 5 is a block diagram illustrating an example of open-block relocation. [0054] With the aggregate of invalid data 506, valid data 508, and dummy data 510 occupying the first eight pages of the first block 500, the FTL may close the first block, then open a second block 550 [0057] In a first example, the FTL may write dummy data 510 up to a partial close block boundary defined by a particular data length to protect previously stored data in the first block 500 and ensure generation of an error code and/or parity for any partially written data.”; the first block, at initial programming, is determined to have 3 open pages, designated by 510 of fig 5; and these 3 pages are written with dummy data).
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 3, 10, 11, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over In in view of Kim, et al, U.S. Patent Application Publication 20150332772 (“Kim”).
Regarding claim 3, In teaches the method of claim 1.
In does not explicitly teach comprising: programming the dummy data as part of a background activity; or performing the flash write operation as part of the background activity.
Kim teaches comprising: programming the dummy data as part of a background activity; or performing the flash write operation as part of the background activity. (Kim, fig 28, “[0195] FIG. 28 is a flow chart schematically illustrating an example of an operation of a memory controller shown in FIG. 27. Referring to FIGS. 27 and 28, in step S410, a memory controller 310 periodically programs dummy data DT_d at a dummy block BLK_d. In exemplary embodiments, the memory controller 310 may program dummy data DT_d at a dummy block BLK_d during a background operation.”; that low priority memory functions can be performed in “background”).
In view of the teachings of Kim it would have been obvious for a person of ordinary skill in the art to apply the teachings of Kim to In before the effective filing date of the claimed invention in order to teach memory erasures. The teachings of Kim, in the same or in a similar field of endeavor with In, can combine Kim’s erasure in the background and In’s less explicit erasure operation. The combined erasure operations merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 10, In teaches the system of claim 9.
In does not explicitly teach wherein, to program the data, the controller is to: program dummy data as part of a background activity.
Kim teaches wherein, to program the data, the controller is to: program dummy data as part of a background activity. (Kim, fig 28, “[0195] FIG. 28 is a flow chart schematically illustrating an example of an operation of a memory controller shown in FIG. 27. Referring to FIGS. 27 and 28, in step S410, a memory controller 310 periodically programs dummy data DT_d at a dummy block BLK_d. In exemplary embodiments, the memory controller 310 may program dummy data DT_d at a dummy block BLK_d during a background operation.”; that low priority memory functions can be performed in “background”).
In view of the teachings of Kim it would have been obvious for a person of ordinary skill in the art to apply the teachings of Kim to In before the effective filing date of the claimed invention in order to teach memory erasures. The teachings of Kim, in the same or in a similar field of endeavor with In, can combine Kim’s erasure in the background and In’s less explicit erasure operation. The combined erasure operations merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 11, In, as modified by Kim, teaches the system of claim 10.
In further teaches wherein, to program the dummy data, the controller is to: program the dummy data on unprogrammed wordlines of the physical block. (In, fig 5, 6, “[0054] Because there is a three open-page gap between the second boundary 504 and the fifth page, the flash translation layer (FTL) may write dummy data 510 into the three open-page gap. With the aggregate of invalid data 506, valid data 508, and dummy data 510 occupying the first eight pages of the first block 500, the FTL may close the first block, then open a second block 550”; that the physical word lines beneath the written data can be written on unprogrammed WLs; in this case 3 WLs of dummy data are written).
Regarding claim 16, In teaches the non-transitory computer-readable medium of claim 15.
In does not explicitly teach wherein, to program the data, the controller is to: program dummy data as part of a background activity.
Kim teaches wherein, to program the data, the controller is to: program dummy data as part of a background activity. (Kim, fig 28, “[0195] FIG. 28 is a flow chart schematically illustrating an example of an operation of a memory controller shown in FIG. 27. Referring to FIGS. 27 and 28, in step S410, a memory controller 310 periodically programs dummy data DT_d at a dummy block BLK_d. In exemplary embodiments, the memory controller 310 may program dummy data DT_d at a dummy block BLK_d during a background operation.”; that low priority memory functions can be performed in “background”).
In view of the teachings of Kim it would have been obvious for a person of ordinary skill in the art to apply the teachings of Kim to In before the effective filing date of the claimed invention in order to teach memory erasures. The teachings of Kim, in the same or in a similar field of endeavor with In, can combine Kim’s erasure in the background and In’s less explicit erasure operation. The combined erasure operations merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 17, In, as modified by Kim, teaches the non-transitory computer-readable medium of claim 16.
In further teaches wherein, to program the dummy data, the controller is to: program the dummy data on unprogrammed wordlines of the physical block. (In, fig 5, 6, “[0054] Because there is a three open-page gap between the second boundary 504 and the fifth page, the flash translation layer (FTL) may write dummy data 510 into the three open-page gap. With the aggregate of invalid data 506, valid data 508, and dummy data 510 occupying the first eight pages of the first block 500, the FTL may close the first block, then open a second block 550”; that the physical word lines beneath the written data can be written on unprogrammed WLs; in this case 3 WLs of dummy data are written).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over In in view of Lee, et al, U.S. Patent Application Publication 2025012375 (“Lee”).
In teaches the method of claim 4.
In does not explicitly teach wherein programming the dummy data comprises: programming data of a random pattern on the unprogrammed wordlines of the physical block.
Lee teaches wherein programming the dummy data comprises: programming data of a random pattern on the unprogrammed wordlines of the physical block. (Lee, fig 1, “[0062] Generally, the flash fill operation writes random dummy data to unprogrammed pages in the block using NAND’s internal mechanisms, creating a closed block state for the subsequent erase operation.”; that dummy data is typically a random style of data).
In view of the teachings of Lee it would have been obvious for a person of ordinary skill in the art to apply the teachings of Lee to In before the effective filing date of the claimed invention in order to teach memory erasures. The teachings of Lee, in the same or in a similar field of endeavor with In, can combine Lee’s explicit random dummy data and In’s dummy data. The combined erasure operations merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over In in view of Yang, et al, U.S. Patent Application Publication 20240161828 (“Yang”).
In teaches the method of claim 4.
In does not explicitly teach wherein programming the dummy data comprises: programming data of a fixed pattern on the unprogrammed wordlines of the physical block.
Yang teaches wherein programming the dummy data comprises: programming data of a fixed pattern on the unprogrammed wordlines of the physical block. (Yang, fig 1, “[0121] In one embodiment, when a sub-block is not storing data, then it is programmed with a random (or not random) data pattern. When the system wants to open a new sub-block in order to store data in that sub-block then the entire sub-block is erased.”; that programming dummy data can comprise random or “not random” data for writing in open pages in a sub-block).
In view of the teachings of Yang it would have been obvious for a person of ordinary skill in the art to apply the teachings of Yang to In before the effective filing date of the claimed invention in order to teach memory erasures. The teachings of Yang, in the same or in a similar field of endeavor with In, can combine Yang’s explicit not random (or random) dummy data and In’s general dummy data. The combined erasure operations merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claims 7, 14, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over In in view of Tsuda, M., U.S. Patent Application Publication 20210043260 (“Tsuda”).
Regarding claim 7, In teaches the method of claim 1.
In does not explicitly teach wherein performing the flash write operation comprises: performing the flash write operation on an entirety of the physical block.
Tsuda teaches wherein performing the flash write operation comprises: performing the flash write operation on an entirety of the physical block. (Tsuda, fig 11, “[0083] FIG. 11 is a flowchart of the first erase flow. In the first erase flow, a flash write operation corresponding to a “first write operation” is executed (S11), [0084] In the flash write operation (S11), a program voltage is applied to all of the word lines WL in the memory block MB to write data of a certain level,”; that in an erase operation, all of the WLs in a block can be subject to a “flash write operation”).
In view of the teachings of Tsuda it would have been obvious for a person of ordinary skill in the art to apply the teachings of Tsuda to In before the effective filing date of the claimed invention in order to teach memory erasures. The teachings of Tsuda, in the same or in a similar field of endeavor with In, can combine Tsuda’s flash write operation on a complete block as part of an erasure operation and In’s writing dummy data to empty pages. The combined erasure operations merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 14, In teaches the system of claim 9.
In does not explicitly teach wherein, to program the data, the controller is to: perform a flash write operation as part of a background activity.
Tsuda teaches wherein, to program the data, the controller is to: perform a flash write operation as part of a background activity. (Tsuda, fig 11, “[0083] FIG. 11 is a flowchart of the first erase flow. In the first erase flow, a flash write operation corresponding to a “first write operation” is executed (S11), [0084] In the flash write operation (S11), a program voltage is applied to all of the word lines WL in the memory block MB to write data of a certain level,”; that in an erase operation, all of the WLs in a block can be subject to a “flash write operation”).
In view of the teachings of Tsuda it would have been obvious for a person of ordinary skill in the art to apply the teachings of Tsuda to In before the effective filing date of the claimed invention in order to teach memory erasures. The teachings of Tsuda, in the same or in a similar field of endeavor with In, can combine Tsuda’s flash write operation on a complete block as part of an erasure operation and In’s writing dummy data to empty pages. The combined erasure operations merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 20, In teaches the non-transitory computer-readable medium of claim 15.
In does not explicitly teach wherein, to program the data, the controller is to: perform a flash write operation as part of a background activity.
Tsuda teaches wherein, to program the data, the controller is to: perform a flash write operation as part of a background activity. (Tsuda, fig 11, “[0083] FIG. 11 is a flowchart of the first erase flow. In the first erase flow, a flash write operation corresponding to a “first write operation” is executed (S11), [0084] In the flash write operation (S11), a program voltage is applied to all of the word lines WL in the memory block MB to write data of a certain level,”; that in an erase operation, all of the WLs in a block can be subject to a “flash write operation”).
In view of the teachings of Tsuda it would have been obvious for a person of ordinary skill in the art to apply the teachings of Tsuda to In before the effective filing date of the claimed invention in order to teach memory erasures. The teachings of Tsuda, in the same or in a similar field of endeavor with In, can combine Tsuda’s flash write operation on a complete block as part of an erasure operation and In’s writing dummy data to empty pages. The combined erasure operations merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claims 12 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over In, as modified by Kim, in view of Lee.
Regarding claim 12, In, as modified by Kim, teaches the system of claim 11.
In, as modified by Kim, does not explicitly teach wherein, to program the dummy data, the controller is to: program data of a random pattern on the unprogrammed wordlines of the physical block.
Lee teaches wherein, to program the dummy data, the controller is to: program data of a random pattern on the unprogrammed wordlines of the physical block. (Lee, fig 1, “[0062] Generally, the flash fill operation writes random dummy data to unprogrammed pages in the block using NAND’s internal mechanisms, creating a closed block state for the subsequent erase operation.”; that dummy data is typically a random style of data).
In view of the teachings of Lee it would have been obvious for a person of ordinary skill in the art to apply the teachings of Lee to In before the effective filing date of the claimed invention in order to teach memory erasures. The teachings of Lee, in the same or in a similar field of endeavor with In, can combine Lee’s explicit random dummy data and In’s dummy data. The combined erasure operations merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 18, In, as modified by Kim, teaches the non-transitory computer-readable medium of claim 17.
In, as modified by Kim, does not explicitly teach wherein, to program the dummy data, the controller is to: program data of a random pattern on the unprogrammed wordlines of the physical block.
Lee teaches wherein, to program the dummy data, the controller is to: program data of a random pattern on the unprogrammed wordlines of the physical block. (Lee, fig 1, “[0062] Generally, the flash fill operation writes random dummy data to unprogrammed pages in the block using NAND’s internal mechanisms, creating a closed block state for the subsequent erase operation.”; that dummy data is typically a random style of data).
In view of the teachings of Lee it would have been obvious for a person of ordinary skill in the art to apply the teachings of Lee to In before the effective filing date of the claimed invention in order to teach memory erasures. The teachings of Lee, in the same or in a similar field of endeavor with In, can combine Lee’s explicit random dummy data and In’s dummy data. The combined erasure operations merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claims 13 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over In, as modified by Kim, in view of Yang.
Regarding claim 13, In, as modified by Kim, teaches the system of claim 11.
In, as modified by Kim, does not explicitly teach wherein, to program the dummy data, the controller is to: program data of a fixed pattern on the unprogrammed wordlines of the physical block.
Yang teaches wherein, to program the dummy data, the controller is to: program data of a fixed pattern on the unprogrammed wordlines of the physical block. (Yang, fig 1, “[0121] In one embodiment, when a sub-block is not storing data, then it is programmed with a random (or not random) data pattern. When the system wants to open a new sub-block in order to store data in that sub-block then the entire sub-block is erased.”; that programming dummy data can comprise random or “not random” data for writing in open pages in a sub-block).
In view of the teachings of Yang it would have been obvious for a person of ordinary skill in the art to apply the teachings of Yang to In before the effective filing date of the claimed invention in order to teach memory erasures. The teachings of Yang, in the same or in a similar field of endeavor with In, can combine Yang’s explicit not random (or random) dummy data and In’s general dummy data. The combined erasure operations merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 19, In, as modified by Kim, teaches the non-transitory computer-readable medium of claim 17.
In, as modified by Kim, does not explicitly teach wherein, to program the dummy data, the controller is to: program data of a fixed pattern on the unprogrammed wordlines of the physical block.
Yang teaches wherein, to program the dummy data, the controller is to: program data of a fixed pattern on the unprogrammed wordlines of the physical block. (Yang, fig 1, “[0121] In one embodiment, when a sub-block is not storing data, then it is programmed with a random (or not random) data pattern. When the system wants to open a new sub-block in order to store data in that sub-block then the entire sub-block is erased.”; that programming dummy data can comprise random or “not random” data for writing in open pages in a sub-block).
In view of the teachings of Yang it would have been obvious for a person of ordinary skill in the art to apply the teachings of Yang to In before the effective filing date of the claimed invention in order to teach memory erasures. The teachings of Yang, in the same or in a similar field of endeavor with In, can combine Yang’s explicit not random (or random) dummy data and In’s general dummy data. The combined erasure operations merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Conclusion
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825
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