DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 17/995,803, filed on 10/07/2022.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 01/26/2026 and 01/15/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-3 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3 and 5 of U.S. Patent No. 12,225,314.
Although the claims at issue are not identical, they are not patentably distinct from each other because the application claims 1-3 are broader, in every aspect, than the Patent claims 1-3 and 5 as shown in the following table.
Regarding claim 1, the subject matter of this claim is met by Patent claims 1 and 3.
Regarding claims 2 and 3, these claims are directly met by Patent claims 2 and 5, respectively.
Application Claims
Patent Claims (US 12,225,314)
1. An imaging device comprising: a plurality of pixel blocks each comprising a plurality of pixels and a memory cell; and a first circuit configured to read out a maximum value of the analog data stored in the memory cell included in each of the plurality of pixel blocks, wherein analog data calculated from data generated by the plurality of pixels is configured to be stored in the memory cell, wherein each of the plurality of pixels comprises a photoelectric conversion device, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a first capacitor, wherein one electrode of the photoelectric conversion device is electrically connected to one of a source and a drain of the first transistor, wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, one electrode of the first capacitor, and a gate of the third transistor, wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor, and wherein the other electrode of the first capacitor is electrically connected to one of a source and a drain of the fifth transistor.
2. The imaging device according to claim 1, wherein the memory cell includes a region overlapping with at least one of the plurality of pixels and the first circuit.
3. An electronic device comprising: the imaging device according to claim 1; and a display device.
1. An imaging device comprising: a plurality of pixel blocks each comprising a plurality of pixels and a memory cell; and a first circuit configured to read out a maximum value of the analog data stored in the memory cell included in each of the plurality of pixel blocks, wherein analog data calculated from data generated by the plurality of pixels is configured to be stored in the memory cell, wherein the memory cell comprises a sixth transistor, a seventh transistor and a second capacitor, and wherein one of a source and a drain of the sixth transistor, one electrode of the second capacitor, and a gate of the seventh transistor are electrically connected to each other.
3. The imaging device according to claim 1, wherein each of the plurality of pixels comprises a photoelectric conversion device, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a first capacitor, wherein one electrode of the photoelectric conversion device is electrically connected to one of a source and a drain of the first transistor, wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, one electrode of the first capacitor, and a gate of the third transistor, wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor, and wherein the other electrode of the first capacitor is electrically connected to one of a source and a drain of the fifth transistor.
2. The imaging device according to claim 1, wherein the memory cell includes a region overlapping with at least one of the plurality of pixels and the first circuit.
5. An electronic device comprising: the imaging device according to claim 1; and a display device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NHAN T TRAN whose telephone number is (571)272-7371. The examiner can normally be reached Monday - Friday, 9:00am - 5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lin Ye can be reached at 571-272-7372. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NHAN T TRAN/Primary Examiner, Art Unit 2638
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