CTNF 19/021,490 CTNF 82222 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This is the initial Office Action based on the application filed 01/15/2025. Claims 21-40 are presented for examination and have been considered below. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-34 AIA Claim s 21-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1-20 of U.S. Patent No. 12,235,722 B2 . Although the claims at issue are not identical, they are not patentably distinct from each other because every limitations claimed in the present application is anticipated by the claimed invention of U.S. Patent No. 12,235,722, as follows: Present application US 12,235,722 B2 21. (New) An apparatus, comprising:a first number of memory units configured to store user data; a second number of memory units that are simultaneously accessible with the first number of memory units and configured to store auxiliary data corresponding to the user data and comprising at least authentication data for protection of data integrity and authenticity of the user data; Anda third number of memory units that are simultaneously accessible with the first number of memory units and the second number of memory units and configured to store parity data corresponding to the user data. 22. (New) The apparatus of claim 21, wherein the parity data corresponds to redundant array of independent disks (RAID) parity data to recover a subset of the user data corresponding to one memory unit of the first number of memory units. 23. (New) The apparatus of claim 21, wherein each memory unit of the first, the second, or the third number of memory units is configured to transfer four bits of data per each beat. 24. (New) The apparatus of claim 21, wherein: a first portion of the first number of memory units corresponds to one double data rate (DDRx) channel; and Application No. 19/021,490 a second portion of the first number of memory units corresponds to a different DDRx channel. 25. (New) The apparatus of claim 21, wherein the apparatus comprises a Compute Express Link (CXL)-compliant memory system that includes the first, the second, and the third number of memory units. 26. (New) The apparatus of claim 25, wherein the memory system is configured to operate according to a CXL protocol. 27. (New) The apparatus of claim 21, wherein the auxiliary data further comprises error detection information generated based on the user data. 28. (New) The apparatus of claim 27, wherein the error detection information corresponds to cyclic redundancy check (CRC) data. 29. (New) The apparatus of claim 21, wherein the authentication data comprises authentication code (MAC) data calculated based on trusted execution environment (TEE) data, host physical address (HPA), or a security key identifier (ID), or any combination thereof. 30. (New) The apparatus of claim 21, wherein the authentication data comprises authentication code (MAC) data corresponding to KECCAK MAC (KAMC). 31. (New) The apparatus of claim 21, wherein the user data corresponds to a unit of host access. 32. (New) An apparatus, comprising:a plurality of memory units; and Application No. 19/021,490 a controller coupled to the plurality of memory units via a plurality of channels, the controller configured to: communicate user data via a plurality of data pins of a first number of memory units of the plurality of memory units; communicate, via a plurality of data pins of a second memory unit of the plurality of memory units, auxiliary data including error detection information simultaneously with the user data to perform an error detection operation on the user data; and communicate, via a plurality of data pins of a third memory unit of the plurality of memory units, parity data to perform an error recovery operation on the user data simultaneously with the user data and the auxiliary data. 33. (New) The apparatus of claim 32, wherein the plurality of data pins of the first number of memory units, the second memory unit, and the third memory unit correspond to data input/output (DQ) pins. 34. (New) The apparatus of claim 32, wherein the controller is configured to communicate the user data, the error detection information, or the parity data at a rate of four bits per beat. 35. (New) The apparatus of claim 32, wherein: the second memory unit corresponds to one double data rate (DDRx) channel; and the third memory unit corresponds to a different DDRx channel. 36. (New) A method, comprising: reading, to execute a host read command to access user data from a first number of memory units, the user data from the first number of memory units via one or more data input/output (DQ) pins of the first number of memory units; reading, simultaneously with reading the user data and to perform an error detection operation on the user data, error detection information corresponding to the user data from a second memory unit; and Application No. 19/021,490 reading, simultaneously with reading the user data and the error detection information and to perform an error recovery operation on the user data, parity data corresponding to the user data from a third memory unit. 37. (New) The method of claim 36, further comprising reading the user data, error detection information, and parity data respectively from each memory unit of the first number of memory units, the second memory unit, and the third memory unit at a rate of four bits per beat. 38. (New) The method of claim 36, further comprising reading, along with the error detection information and simultaneously with reading the user data and from the second memory unit of, authentication data generated based on the user data. 39. (New) The method of claim 38, wherein the user data is encrypted prior to being stored to the first number of memory units, and the method further comprises: decrypting the user data; and performing, responsive to the user data being decrypted, an authentication operation on the user data using the authentication data. 40. (New) The method of claim 36, further comprising: performing an error detection operation on the user data using the error detection information to indicate whether the user data includes a number of errors; performing an error recovery operation on the user data using the parity data to recover the user data and responsive to the error detection operation indicating the number of errors in the user data; and bypassing performance of the error recovery operation responsive to the error detection operation not indicating the number of errors in the user data. 1. An apparatus, comprising: a first number of memory units configured to store a user data block (UDB) corresponding to a unit of host access; a second number of memory units that are simultaneously accessible with the first number of memory units and configured to store auxiliary data corresponding to the UDB and comprising at least authentication data for protection of data integrity and authenticity of the UDB; and a third number of memory units that are simultaneously accessible with the first number of memory units and the second number of memory units and configured to store parity data corresponding to the UDB. 2. The apparatus of claim 1, wherein the parity data corresponds to redundant array of independent disks (RAID) parity data to recover a subset of the UDB corresponding to one memory unit of the first number of memory units. 3. The apparatus of claim 1, wherein each memory unit of the first, the second, or the third number of memory units is configured to transfer four bits of data per each beat. 4. The apparatus of claim 1, wherein: a first portion of the first number of memory units corresponds to one double data rate (DDRx) channel; and a second portion of the first number of memory units corresponds to a different DDRx channel. 5. The apparatus of claim 1, wherein the apparatus comprises a Compute Express Link (CXL)-compliant memory system that includes the first, the second, and the third number of memory units. 6. The apparatus of claim 5, wherein the memory system is configured to operate according to a CXL 3.0 protocol. 7. The apparatus of claim 1, wherein the auxiliary data further comprises error detection information generated based on the UDB. 8. The apparatus of claim 7, wherein the error detection information corresponds to cyclic redundancy check (CRC) data. 9. The apparatus of claim 1, wherein the authentication data comprises authentication code (MAC) data. 10. The apparatus of claim 1, wherein each memory unit of the first number of memory units, the second memory unit, and the third memory unit corresponds to a memory die. 11. An apparatus, comprising: a plurality of memory units; and a controller coupled to the plurality of memory units via a plurality of channels, the controller configured to: exchange a user data block (UDB) via a plurality of data pins of a first number of memory units of the plurality of memory units; exchange, via a plurality of data pins of a second memory unit of the plurality of memory units, auxiliary data including error detection information simultaneously with the UDB to perform an error detection operation on the UDB; and exchange, via a plurality of data pins of a third memory unit of the plurality of memory units, a parity data block (PDB) to perform an error recovery operation on the UDB simultaneously with the UDB and the auxiliary data. 12. The apparatus of claim 11, wherein the plurality of data pins of the first number of memory units, the second memory unit, and the third memory unit correspond to data input/output (DQ) pins. 13. The apparatus of claim 11, wherein the controller is configured to exchange the UDB, the error detection information, or the PDB at a rate of four bits per beat. 14. The apparatus of claim 11, wherein: the second memory unit corresponds to one double data rate (DDRx) channel; and the third memory unit corresponds to a different DDRx channel. 15. The apparatus of claim 11, wherein the controller is configured to: exchange 64 bytes of the UDB via the plurality of data pins of the first number of memory units; exchange 64 bits of the auxiliary data via the plurality of data pins of the second memory unit. 16. A method, comprising: receiving a host read command to access an UDB from a first number of memory units; reading the UDB from the first number of memory units via one or more data input/output (DQ) pins of the first number of memory units; reading, simultaneously with reading the UDB and to perform an error detection operation on the UDB, error detection information corresponding to the UDB from a second memory unit; and reading, simultaneously with reading the UDB and the error detection information and to perform an error recovery operation on the UDB, a parity data block (PDB) containing redundant array of independent disks (RAID) parity data corresponding to the UDB from a third memory unit. 17. The method of claim 16, further comprising reading the UDB, error detection information, and PDB respectively from each memory unit of the first number of memory units, the second memory unit, and the third memory unit at a rate of four bits per beat. 18. The method of claim 16, further comprising reading, along with the error detection information and simultaneously with reading the UDB and from the second memory unit of the number of memory units, authentication data generated based on the UDB. 19. The method of claim 18, wherein the UDB is encrypted prior to being stored to the first number of memory units, and the method further comprises: decrypting the UDB; and performing, responsive to the UDB being decrypted, an authentication operation on the UDB. 20. The method of claim 16, further comprising: performing an error detection operation on the UDB using the error detection information to indicate whether the UDB includes a number of errors; performing an error recovery operation on the UDB using the RAID parity data of the PDB to recover the UDB and responsive to the error detection operation indicating the number of errors in the UDB; and bypassing performance of the error recovery operation responsive to the error detection operation not indicating the number of errors in the UDB . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim (s) 21-23, 27-34, 36-39 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US2023/0342174 A1) and further in view of Saileshwar (US 2019/0043600 A1) . Claim 21: Yang teaches an apparatus, comprising: a first number of memory units configured to store user data (e.g., logical storage units storing data in a distributed storage system- [0038]); and a third number of memory units that are simultaneously accessible (e.g., multiple disks accessible in parallel through distributed storage architecture – [0031] ) with the first number of memory units and configured to store parity data corresponding to the user data (e.g., [0062]-[0072]; [0093], RAID redundancy inherently involve parity concepts for recovering data after disk failure). Yang fails to teach a second number of memory units that are simultaneously accessible with the first number of memory units and configured to store auxiliary data corresponding to the user data and comprising at least authentication data for protection of data integrity and authenticity of the user data. However, Saileshwar teaches second number of memory units (metadata chips) storing auxiliary data (e.g., Figs. 1, 5; col. 2, lines 15-23 – memory module with eight data chips C0-C7 and two metadata chips ECC1, ECC2), wherein the second number of memory units are simultaneous accessible with first memory units (e.g. Abstract - data, MAC and ECC can be retrieved together in a single read transaction). Saileshwar further teaches auxiliary data comprising authentication data for integrity/authenticity (e.g., col. 3, lines 4-7 – Message Authentication Code (MAC) generated using cryptographic hash (AES-GCM, SHA-256) to detect tampering and verify authenticity). Therefore, it would have been obvious to a POSITA, before the effective filing date of the claimed invention, to combine Saileshwar ’s authentication metadata with Yang ’s RAID parity to achieve both security (tamper detection) and reliability (hardware fault tolerance). As per claims 32 and 36, the claimed features are rejected similarly to claim 21 above. Claim 22: Yang and Saileshwar teach the apparatus of claim 21, wherein the parity data corresponds to redundant array of independent disks (RAID) parity data to recover a subset of the user data corresponding to one memory unit of the first number of memory units. (e.g. Yang: [0064]-[0072] – RAID parity recovery for disk failures.). Claim 23: Yang and Saileshwar teach the apparatus of claim 21, but fail to teach that each memory unit of the first, the second, or the third number of memory units is configured to transfer four bits of data per each beat. However, it would have been obvious to a POSITA to adjust the memory size in Yang and Saileshwar , since such a modification would have involved a routine design choice and would have been within the general knowledge of an artisan in the art. As per claims 34 and 37, the claimed features are rejected similarly to claim 23 above. Claim 27: Yang and Saileshwar teach the apparatus of claim 21, wherein the auxiliary data further comprises error detection information generated based on the user data ( Saileshwar : col. 2, lines 15-23 – memory module with eight data chips C0-C7 and two metadata chips ECC1, ECC2). Claim 28: Yang and Saileshwar teach the apparatus of claim 27, but fail to teach that the error detection information corresponds to cyclic redundancy check (CRC) data. However, it would have been obvious to a POSITA to use any known error detection/correction technique in the teaching of Yang and Saileshwar, since such a modification would have involved applying a known technique to a known device (method, or product) ready for improvement to yield predictable results. Claim 29: Yang and Saileshwar teach the apparatus of claim 21, wherein the authentication data comprises authentication code (MAC) data calculated based on trusted execution environment (TEE) data, host physical address (HPA), or a security key identifier (ID), or any combination thereof (e.g., Saileshwar: col. 3, lines 35-44). Claim 30: Yang and Saileshwar teach the apparatus of claim 21, but fail to teach that the authentication data comprises authentication code (MAC) data corresponding to KECCAK MAC (KAMC). However, it would have been obvious to a POSITA to use any known error cryptographic technique in the teaching of Yang and Saileshwar, since such a modification would have involved applying a known technique to a known device (method, or product) ready for improvement to yield predictable results. Claim 31: Yang and Saileshwar teach the apparatus of claim 21, wherein the user data corresponds to a unit of host access (e.g. Yang: [0031]). Claim 33: Yang and Saileshwar teach the apparatus of claim 32, wherein the plurality of data pins of the first number of memory units, the second memory unit, and the third memory unit correspond to data input/output (DQ) pins (e.g., Inherent in DIMM interface). Claim 38: Yang and Saileshwar teach the method of claim 36, further comprising reading, along with the error detection information and simultaneously with reading the user data and from the second memory unit of, authentication data generated based on the user data (e.g., Saileshwar : col. 3, lines 4-7). Claim 39: Yang and Saileshwar teach the method of claim 38, wherein the user data is encrypted prior to being stored to the first number of memory units, and the method further comprises: decrypting the user data; and performing, responsive to the user data being decrypted, an authentication operation on the user data using the authentication data (e.g., Saileshwar : col. 3, lines 14-34) . 07-22-aia AIA Claim (s) 24 and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Yang and Saileshwar as applied to claim 21 above, and further in view of Berke (US2016/0179374 A1) . Claim 24: Yang and Saileshwar teach the apparatus of claim 21, but fail to teach that a first portion of the first number of memory units corresponds to one double data rate (DDRx) channel; and a second portion of the first number of memory units corresponds to a different DDRx channel. However, the technique of using different types of memory devices (e.g., DDR) in a memory circuit was known in the art, before the effective filing date of the claimed invention, as disclosed by Berke (e.g., [0021], [0026]). Therefore, it would have been obvious to a POSITA to implement the teaching of Yang and Saileshwar with the one disclosed by B erke , since such a modification would have involved applying a known technique to a known device (method, or product) ready for improvement to yield predictable results. As per claim 35, the claimed features are rejected similarly to claim 24 above . 07-22-aia AIA Claim (s) 25, 26 are rejected under 35 U .S.C. 103 as being unpatentable over Yang and Saileshwar as applied to claim 21 above, and further in view of Das Sharma et al (US2021/0119730 A1) . Claim 25: Yang and Saileshwar teach the apparatus of claim 21, but fail to teach that the apparatus comprises a Compute Express Link (CXL)-compliant memory system that includes the first, the second, and the third number of memory units. However, such a technique was known in the art, before the effective filing date of the claimed invention, as disclosed by Das Sharma et al (e.g. [0055]).Therefore, it would have been obvious to a POSITA to implement the teaching of Yang and Saileshwar with the one disclosed by Das Sharma et al, since such a modification would have involved applying a known technique to a known device (method, or product) ready for improvement to yield predictable results. Claim 26: Yang and Saileshwar in view of Das Sharma et al teach the apparatus of claim 25, wherein the memory system is configured to operate according to a CXL protocol (e.g., [0055] - Das Sharma et al) . 07-22-aia AIA Claim (s) 40 is rejected under 35 U.S.C. 103 as being unpatentable over Yang and Saileshwar as applied to claim 36 above, and further in view of Thompson et al (US2023/0236913 A1) . Claim 40: Yang and Saileshwar teach the method of claim 36, further comprising: performing an error detection operation on the user data using the error detection information to indicate whether the user data includes a number of errors (e.g. col. 2, lines 30-33 - Saileshwar ); performing an error recovery operation on the user data using the parity data to recover the user data and responsive to the error detection operation indicating the number of errors in the user data (e.g. [0064]-[0068] – Yang). Yang and Saileshwar fail to teach that bypassing performance of the error recovery operation responsive to the error detection operation not indicating the number of errors in the user data. However, such a technique was known in the art, before the effective filing date of the claimed invention as disclosed by Thompson et al (e.g., [0004]). Therefore, it would have been obvious to a POSITA to implement the teaching of Yang and Saileshwar with the one disclosed by Thompson et al since data recovery is unnecessary if no error is detected. Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUERRIER MERANT whose telephone number is (571)270-1066. The examiner can normally be reached Monday-Friday 8:00 Am - 5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at 571-270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GUERRIER MERANT/Primary Examiner, Art Unit 2111 4/30/2026 Application/Control Number: 19/021,490 Page 2 Art Unit: 2111 Application/Control Number: 19/021,490 Page 3 Art Unit: 2111 Application/Control Number: 19/021,490 Page 4 Art Unit: 2111 Application/Control Number: 19/021,490 Page 5 Art Unit: 2111 Application/Control Number: 19/021,490 Page 6 Art Unit: 2111 Application/Control Number: 19/021,490 Page 7 Art Unit: 2111 Application/Control Number: 19/021,490 Page 8 Art Unit: 2111 Application/Control Number: 19/021,490 Page 9 Art Unit: 2111 Application/Control Number: 19/021,490 Page 10 Art Unit: 2111 Application/Control Number: 19/021,490 Page 11 Art Unit: 2111 Application/Control Number: 19/021,490 Page 12 Art Unit: 2111 Application/Control Number: 19/021,490 Page 13 Art Unit: 2111 Application/Control Number: 19/021,490 Page 14 Art Unit: 2111 Application/Control Number: 19/021,490 Page 15 Art Unit: 2111 Application/Control Number: 19/021,490 Page 16 Art Unit: 2111 Application/Control Number: 19/021,490 Page 17 Art Unit: 2111 Application/Control Number: 19/021,490 Page 18 Art Unit: 2111 Application/Control Number: 19/021,490 Page 19 Art Unit: 2111 Application/Control Number: 19/021,490 Page 20 Art Unit: 2111 Application/Control Number: 19/021,490 Page 21 Art Unit: 2111 Application/Control Number: 19/021,490 Page 22 Art Unit: 2111 Application/Control Number: 19/021,490 Page 23 Art Unit: 2111 Application/Control Number: 19/021,490 Page 25 Art Unit: 2111 Application/Control Number: 19/021,490 Page 26 Art Unit: 2111
Prosecution Insights