Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 and 12-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Han et al (2016/0064098) in view of Xu et al (2023/0129629) hereinafter, Xu.
In regards to claim 1, Han teaches a driving circuit comprising a plurality of stages, each of the plurality of stages comprising (abstract):
a first transistor (fig. 5b T311) connected between a first node (fig. 5b node FD connection between T311 and T312)) and a first terminal to which a start signal is input (fig. 5b STV), the first transistor comprising (fig. 5b (T311))
a gate connected to a first clock terminal to which a first clock signal is input (fig 5b (CLK and T311));
a second transistor connected between the first node (fig. 5b FD between T311 and T312)) and a second node (fig. 5b Q1), the second transistor comprising(fig. 5b T312))
a gate connected to the first clock terminal (fig. 5b (CLK and T312))
a third transistor connected between the first node and a second clock terminal to which a second clock signal is input, the third transistor comprising (fig. 5b T331 between CLKB node FB). Examiner notes T3331 is connected between FD node through Q1 and T312 to CLKB (MPEP 2111). Furthermore, the circuit will function equivalent because the node FD and Q1 will be at the same potential when CLK is applied since T312 is turned on.
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a gate connected to the first node fig. 5b Q1)
Han fails to teach a first capacitor connected between the third transistor and the first node, with respect to a second capacitor as claimed. Examiner notes (fig. C1 connected at Q1 between FD and T331 C1);
However, Xu teaches a first capacitor connected between the third transistor and the first node. (fig. 2 (Cp) [0077] Xu)
[0077] It should be noted that, in the T2 time period, signals of the second clock signal line CK2 is directly transmitted to the cascade signal output terminal 61 through the first transistor T1, and the capacitor Cp will not cause loss to signals transmitted to the cascade signal output terminal 61, so as to ensure that the cascade signal output terminal 61 outputs stable cascade signals. In addition, in the T3 time period and the time period after T3, cascade signals output from the cascade signal output terminal 61 is always maintained at a low level by the second low-voltage signal line VL2, which can prevent an abnormal run out of the cascade signals output from the cascade signal output terminal 61 due to a signal fluctuation of the second clock signal line CK2.
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It would have been obvious to one of ordinary skill in the art to modify the teachings of Han to further include a first capacitor connected between the third transistor and the first node which can help with loss of signal and fluctuations with the second clock signal.
Therefore, Han in view of Xu teaches
a first capacitor connected between the third transistor and the first node (fig. 2 (Cp) [0077] Xu)
a fourth transistor connected between an output terminal and a second terminal to which a first voltage is applied, the fourth transistor comprising (fig. 5b T342))Han:
a gate connected to the first clock terminal (fig 5b.gate of T342)Han; and
a fifth transistor connected between the output terminal and the second clock terminal, the fifth transistor comprising: a gate connected to the second node (fig. 5b (T341 and CLKB and Q1) Han.
In regards to claim 12, Han teaches a driving circuit comprising a plurality of stages, each of the plurality of stages comprising: a first transistor connected between a first node and a first terminal to which a start signal is input,(fig. 5b T311) the first transistor comprising: a gate connected to a first clock terminal to which a first clock signal is input (fig. 5b T311 and CLK); a second transistor connected between the first node and a second node (fig. 5b T312 between FD and Q1), the second transistor comprising: a gate connected to the first clock terminal (fig. 5b T312 connected to CLK); a third transistor connected between the first node and a second clock terminal to which a second clock signal is input (fig. 5b T331 CLKB and FD), the third transistor comprising: a gate connected to the first node (fig. 5b T331 and CLKB between FB);
Han fails to teach a first capacitor connected between the third transistor and the first node, with respect to a second capacitor as claimed. Examiner notes (fig. C1 connected at Q1 between FD and T331 C1);
However, Xu teaches a first capacitor connected between the third transistor and the first node. (fig. 2 (Cp) [0077] Xu)
It would have been obvious to one of ordinary skill in the art to modify the teachings of Han to further include a first capacitor connected between the third transistor and the first node which can help with loss of signal and fluctuations with the second clock signal.
Therefore, Han in view of Xu teaches a second capacitor connected between the second node and an output terminal (fig. 5b C2 VGL and Q1 through components) Han); and
a fourth transistor connected between the output terminal and the second clock terminal, the fourth transistor comprising: (fig. 5b T342 Han)):
a gate connected to the second node (fig. 5b node Q1 Han), and
wherein the third transistor and the first capacitor change a voltage of the first node in synchronization with a voltage change of the second node [166] Han in view (fig. 2 (Cp) [0077] Xu).
In regards to claim 2, Han in view of Xu teaches the driving circuit of claim 1, wherein the start signal comprises an external signal or an output signal output by a previous stage of each of the plurality of stages (fig. 7 stv from outside shift register in first stage and stv from previous stage Han).
In regards to claim 3, Han in view of Xu teaches the driving circuit of claim 1, wherein each of the plurality of stages further comprises: a second capacitor connected between the second node and a third terminal to which a second voltage which is lower than the first voltage is applied (fig. 5b C2 VGL and Q1 through components) Han; and a third capacitor connected between the second node and the output terminal (fig. 5b (C1 OUTc and Q1) Han.
In regards to claim 4, Han in view of Xu teaches driving circuit of claim 3, wherein the first clock signal and the second clock signal alternately repeat a first voltage level of the first voltage and a second voltage level of the second voltage, and the second clock signal is input by being shifted a ½ cycle from the first clock signal. (fig. 6b CLK and CLKB) Han.
In regards to claim 13, Han in view of Xu teaches driving circuit of claim 12, wherein the start signal comprises an external signal or an output signal output by a previous stage of each of the plurality of stages. (fig. 7 stv from outside shift register in first stage and stv from previous stage Han).
In regards to claim 14, Han in view of Xu teaches driving circuit of claim 12, wherein the first clock signal and the second clock signal alternately repeat a first voltage level and a second voltage level which is lower than the first voltage level, and the second clock signal is input by being shifted a ½ cycle from the first clock signal (fig. 6b CLK and CLKB) Han.
In regards to claim 15, Han in view of Xu teaches driving circuit of claim 14, wherein each of the plurality of stages further comprises: a fifth transistor connected between the output terminal and a second terminal to which a first voltage of the first voltage level is applied (fig. 5b (T342) Han, and comprising a gate connected to the first clock terminal (fig. 5b T342 and CLK) Han; and a third capacitor connected between the second node and a third terminal to which a second voltage of the second voltage level is applied (fig. 5b C1)) Han.
Allowable Subject Matter
Claims 5-11 and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/GRANT SITTA/Primary Examiner, Art Unit 2622