DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Claims 2-21 are pending.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2, 8, and 15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 12, and 15 of U.S. Patent No. 94176787. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 2, 8, and 15 of the instant application are anticipated by patent claims 1, 12, and 15, respectively in that the patent claims contain all the limitations of the instant application.
Claim 2 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 2 of U.S. Patent No. 10241563. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 2 of the instant application are anticipated by patent claims 1 and 2, respectively in that the patent claims contain all the limitations of the instant application.
Claim 8 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 6-7 of U.S. Patent No. 10241563. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 8 of the instant application are anticipated by patent claims 6-7, respectively in that the patent claims contain all the limitations of the instant application.
Claim 15 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 16 of U.S. Patent No. 10241563. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 15 of the instant application are anticipated by patent claims 16, respectively in that the patent claims contain all the limitations of the instant application.
Claim 2 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2 and 6 of U.S. Patent No. 12656854. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 2 of the instant application are anticipated by patent claims 1-2 and 6, respectively in that the patent claims contain all the limitations of the instant application.
Claim 8 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 8-9 and 14 of U.S. Patent No. 12656854. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 8 of the instant application are anticipated by patent claims 8-9 and 14, respectively in that the patent claims contain all the limitations of the instant application.
Claim 15 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 15-16, and 18 of U.S. Patent No. 12656854. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 15 of the instant application are anticipated by patent claims 15-16, and 18, respectively in that the patent claims contain all the limitations of the instant application.
Claims 2, 8, and 15 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 and 5 of U.S. Patent No. 10739841 in view of Kapil et al. (US 20100316065).
Although the claims at issue are not identical, they are not patentably distinct from each other because claims 2, 8, and 15 of the instant application is obvious by patent claim 1 and 5 of US 10739841 and in view of Kapil et al. (US 20100316065) in that the patent claims contain all the limitations of the instant application.
US 10739841 and Kapil are analogous art. Kapil is cited to teach a common signaling rate used for both bandwidth modes. Based on Kapil, it would have been obvious at the time the invention was invented to a person having ordinary skill in the art to which said subject matter pertains to have modified US 10739841 to use a sane signaling rate used for both bandwidth modes. Furthermore, being able to maintain a same signaling rate used for both bandwidth modes improves on US 10739841 by being able to maintain calibration not changing the clock rate with different bandwidths. To one of ordinary skill in the art at the time the invention was filed would it would have been advantageous to make this modification because it improves overall system performance by being able to maintain calibration of the bus.
Instant Application
US 10739841
Kapil et al.
Claim 8: A first integrated circuit, comprising: a plurality of link interfaces, at least one of the plurality of link interfaces to receive, from a second integrated circuit, a first bandwidth mode indicator via a first control packet, and a second bandwidth mode indicator via a second control packet;
Claim 1: A memory integrated circuit device, comprising: a plurality of control receiver circuits to receive, from a memory controller and via a plurality of control signaling links, control information that includes first control information; a plurality of transmitter circuits to transfer data to the memory controller via a plurality of data signaling links, wherein the first control information provides an indication of how many of the data signaling links are employed to transfer the data; a first steering circuit to select between concurrently routing the data across all of the transmitter circuits if all of the transmitter circuits are enabled and to employ at least partial serialization to route the data to a first subset of the transmitter circuits if a second subset of the transmitter circuits is disabled
Claim 5: wherein the control signals are generated as a result of receiving, from the memory controller, a signal that the memory integrated circuit device is to transition between a lower power mode and a higher power mode.
and mode circuitry to, based on the first bandwidth mode indicator, operate the plurality of link interfaces in a first bandwidth mode that transfers data via each of the plurality of link interfaces,
Claim 1: A memory integrated circuit device, comprising: a plurality of control receiver circuits to receive, from a memory controller and via a plurality of control signaling links, control information that includes first control information; a plurality of transmitter circuits to transfer data to the memory controller via a plurality of data signaling links, wherein the first control information provides an indication of how many of the data signaling links are employed to transfer the data; a first steering circuit to select between concurrently routing the data across all of the transmitter circuits if all of the transmitter circuits are enabled and to employ at least partial serialization to route the data to a first subset of the transmitter circuits if a second subset of the transmitter circuits is disabled
wherein each link interface of the plurality of link interfaces is to each respectively transfer data at a same signaling rate,
[0063], “each threshold is associated with a specified number of lanes to be used to transmit frames on the SERDES link 110. For example, assuming an embodiment that uses a single threshold, N, a predetermined number of lanes, M, can be used for transmitting frames when bandwidth demand is at or above N, while a second predetermined number of lanes, K, can be used for transmitting frames when bandwidth demand is below N. More specifically, in an embodiment that includes 16 lanes and has a single threshold set at 50% of typical link bandwidth, 16 lanes can be used to transmit frames when bandwidth demand is at or above 50% of typical bandwidth, while 12, 10, 8, 4, 2, or 1 lane can be used to transfer data when bandwidth demands are below 50%.” [0086], “assuming an embodiment that includes 16 lanes in a SERDES link, 8 lanes, 4 lanes, or 2 lanes can be used, which causes the frames to be sent in two clock cycles (i.e., in 24 ticks for a TX 204 that can send 12 cells on a lane per clock cycle), four clock cycles, or eight clock cycles, respectively.”
the mode circuitry also to, based on the second bandwidth mode indicator, operate the plurality of link interfaces in a second bandwidth mode that transfers data via each of a subset of the plurality of link interfaces,
Claim 1: A memory integrated circuit device, comprising: a plurality of control receiver circuits to receive, from a memory controller and via a plurality of control signaling links, control information that includes first control information; a plurality of transmitter circuits to transfer data to the memory controller via a plurality of data signaling links, wherein the first control information provides an indication of how many of the data signaling links are employed to transfer the data; a first steering circuit to select between concurrently routing the data across all of the transmitter circuits if all of the transmitter circuits are enabled and to employ at least partial serialization to route the data to a first subset of the transmitter circuits if a second subset of the transmitter circuits is disabled
Claim 5: wherein the control signals are generated as a result of receiving, from the memory controller, a signal that the memory integrated circuit device is to transition between a lower power mode and a higher power mode.
wherein each link interface of the subset of the plurality of link interfaces is to each respectively transfer data at the same signaling rate.
[0063], “each threshold is associated with a specified number of lanes to be used to transmit frames on the SERDES link 110. For example, assuming an embodiment that uses a single threshold, N, a predetermined number of lanes, M, can be used for transmitting frames when bandwidth demand is at or above N, while a second predetermined number of lanes, K, can be used for transmitting frames when bandwidth demand is below N. More specifically, in an embodiment that includes 16 lanes and has a single threshold set at 50% of typical link bandwidth, 16 lanes can be used to transmit frames when bandwidth demand is at or above 50% of typical bandwidth, while 12, 10, 8, 4, 2, or 1 lane can be used to transfer data when bandwidth demands are below 50%.” [0086], “assuming an embodiment that includes 16 lanes in a SERDES link, 8 lanes, 4 lanes, or 2 lanes can be used, which causes the frames to be sent in two clock cycles (i.e., in 24 ticks for a TX 204 that can send 12 cells on a lane per clock cycle), four clock cycles, or eight clock cycles, respectively.”
Claims 2, 8, and 15 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 and 3 of U.S. Patent No. 11474590 in view of Kapil et al. (US 20100316065).
Although the claims at issue are not identical, they are not patentably distinct from each other because claims 2, 8, and 15 of the instant application is obvious by patent claim 1 and 3 of US 11474590 and in view of Kapil et al. (US 20100316065) in that the patent claims contain all the limitations of the instant application.
US 11474590 and Kapil are analogous art. Kapil is cited to teach a common signaling rate used for both bandwidth modes. Based on Kapil, it would have been obvious at the time the invention was invented to a person having ordinary skill in the art to which said subject matter pertains to have modified US 11474590 to use a sane signaling rate used for both bandwidth modes. Furthermore, being able to maintain a same signaling rate used for both bandwidth modes improves on US 11474590 by being able to maintain calibration not changing the clock rate with different bandwidths. To one of ordinary skill in the art at the time the invention was filed would it would have been advantageous to make this modification because it improves overall system performance by being able to maintain calibration of the bus.
Instant Application
US 11474590
Kapil et al.
Claim 8: A first integrated circuit, comprising: a plurality of link interfaces, at least one of the plurality of link interfaces to receive, from a second integrated circuit, a first bandwidth mode indicator via a first control packet, and a second bandwidth mode indicator via a second control packet;
Claim 1: An integrated circuit, comprising: a data interface to communicate data with a memory device using a plurality of data interface circuits; and, a control interface to transmit a plurality of control packets to the memory device using a plurality of control driver circuits, the plurality of control packets including a first indicator of a first subset of the data interface circuits to be enabled and a second subset of the data interface circuits to be disabled, the first indicator to be transmitted in a first one of the plurality of control packets in association with a first command
Claim 3: wherein a second indicator transmitted in association with a second command of the plurality of commands transmitted by the plurality of control packets indicates the first subset of the data interface circuits are to be enabled and the second subset of the data interface circuits are to be disabled.
and mode circuitry to, based on the first bandwidth mode indicator, operate the plurality of link interfaces in a first bandwidth mode that transfers data via each of the plurality of link interfaces,
a control interface to transmit a plurality of control packets to the memory device using a plurality of control driver circuits, the plurality of control packets including a first indicator of a first subset of the data interface circuits to be enabled and a second subset of the data interface circuits to be disabled, the first indicator to be transmitted in a first one of the plurality of control packets in association with a first command
wherein each link interface of the plurality of link interfaces is to each respectively transfer data at a same signaling rate,
[0063], “each threshold is associated with a specified number of lanes to be used to transmit frames on the SERDES link 110. For example, assuming an embodiment that uses a single threshold, N, a predetermined number of lanes, M, can be used for transmitting frames when bandwidth demand is at or above N, while a second predetermined number of lanes, K, can be used for transmitting frames when bandwidth demand is below N. More specifically, in an embodiment that includes 16 lanes and has a single threshold set at 50% of typical link bandwidth, 16 lanes can be used to transmit frames when bandwidth demand is at or above 50% of typical bandwidth, while 12, 10, 8, 4, 2, or 1 lane can be used to transfer data when bandwidth demands are below 50%.” [0086], “assuming an embodiment that includes 16 lanes in a SERDES link, 8 lanes, 4 lanes, or 2 lanes can be used, which causes the frames to be sent in two clock cycles (i.e., in 24 ticks for a TX 204 that can send 12 cells on a lane per clock cycle), four clock cycles, or eight clock cycles, respectively.”
the mode circuitry also to, based on the second bandwidth mode indicator, operate the plurality of link interfaces in a second bandwidth mode that transfers data via each of a subset of the plurality of link interfaces,
Claim 3: wherein a second indicator transmitted in association with a second command of the plurality of commands transmitted by the plurality of control packets indicates the first subset of the data interface circuits are to be enabled and the second subset of the data interface circuits are to be disabled.
wherein each link interface of the subset of the plurality of link interfaces is to each respectively transfer data at the same signaling rate.
[0063], “each threshold is associated with a specified number of lanes to be used to transmit frames on the SERDES link 110. For example, assuming an embodiment that uses a single threshold, N, a predetermined number of lanes, M, can be used for transmitting frames when bandwidth demand is at or above N, while a second predetermined number of lanes, K, can be used for transmitting frames when bandwidth demand is below N. More specifically, in an embodiment that includes 16 lanes and has a single threshold set at 50% of typical link bandwidth, 16 lanes can be used to transmit frames when bandwidth demand is at or above 50% of typical bandwidth, while 12, 10, 8, 4, 2, or 1 lane can be used to transfer data when bandwidth demands are below 50%.” [0086], “assuming an embodiment that includes 16 lanes in a SERDES link, 8 lanes, 4 lanes, or 2 lanes can be used, which causes the frames to be sent in two clock cycles (i.e., in 24 ticks for a TX 204 that can send 12 cells on a lane per clock cycle), four clock cycles, or eight clock cycles, respectively.”
Claims 2, 8, and 15 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 2 of U.S. Patent No. 11886272 in view of Kapil et al. (US 20100316065).
Although the claims at issue are not identical, they are not patentably distinct from each other because claims 2, 8, and 15 of the instant application is obvious by patent claim 1 of US 11886272 and in view of Kapil et al. (US 20100316065) in that the patent claims contain all the limitations of the instant application.
US 11886272 and Kapil are analogous art. Kapil is cited to teach a common signaling rate used for both bandwidth modes. Based on Kapil, it would have been obvious at the time the invention was invented to a person having ordinary skill in the art to which said subject matter pertains to have modified US 11886272 to use a sane signaling rate used for both bandwidth modes. Furthermore, being able to maintain a same signaling rate used for both bandwidth modes improves on US 11886272 by being able to maintain calibration not changing the clock rate with different bandwidths. To one of ordinary skill in the art at the time the invention was filed would it would have been advantageous to make this modification because it improves overall system performance by being able to maintain calibration of the bus.
Instant Application
US 11886272
Kapil et al.
Claim 8: A first integrated circuit, comprising: a plurality of link interfaces, at least one of the plurality of link interfaces to receive, from a second integrated circuit, a first bandwidth mode indicator via a first control packet, and a second bandwidth mode indicator via a second control packet;
Claim 1: A memory device, comprising: a plurality of control receiver circuits to receive control information including first control information and second control information; a plurality of data transmitter circuits to transmit data stored in a memory array to a controller; and a first steering circuit coupled to the memory array and the plurality of data transmitter circuits,
and mode circuitry to, based on the first bandwidth mode indicator, operate the plurality of link interfaces in a first bandwidth mode that transfers data via each of the plurality of link interfaces,
based on the first control information received via the plurality of control receiver circuits, select between concurrently routing data received from the memory array across all of the plurality of data transmitter circuits when all of the plurality of data transmitter circuits are enabled and to employ at least partial serialization to route the data received from the memory array to a first subset of the plurality of data transmitter circuits when a second subset of the plurality of data transmitter circuits are disabled in response to the first control information
wherein each link interface of the plurality of link interfaces is to each respectively transfer data at a same signaling rate,
[0063], “each threshold is associated with a specified number of lanes to be used to transmit frames on the SERDES link 110. For example, assuming an embodiment that uses a single threshold, N, a predetermined number of lanes, M, can be used for transmitting frames when bandwidth demand is at or above N, while a second predetermined number of lanes, K, can be used for transmitting frames when bandwidth demand is below N. More specifically, in an embodiment that includes 16 lanes and has a single threshold set at 50% of typical link bandwidth, 16 lanes can be used to transmit frames when bandwidth demand is at or above 50% of typical bandwidth, while 12, 10, 8, 4, 2, or 1 lane can be used to transfer data when bandwidth demands are below 50%.” [0086], “assuming an embodiment that includes 16 lanes in a SERDES link, 8 lanes, 4 lanes, or 2 lanes can be used, which causes the frames to be sent in two clock cycles (i.e., in 24 ticks for a TX 204 that can send 12 cells on a lane per clock cycle), four clock cycles, or eight clock cycles, respectively.”
the mode circuitry also to, based on the second bandwidth mode indicator, operate the plurality of link interfaces in a second bandwidth mode that transfers data via each of a subset of the plurality of link interfaces,
based on the first control information received via the plurality of control receiver circuits, select between concurrently routing data received from the memory array across all of the plurality of data transmitter circuits when all of the plurality of data transmitter circuits are enabled and to employ at least partial serialization to route the data received from the memory array to a first subset of the plurality of data transmitter circuits when a second subset of the plurality of data transmitter circuits are disabled in response to the first control information
wherein each link interface of the subset of the plurality of link interfaces is to each respectively transfer data at the same signaling rate.
[0063], “each threshold is associated with a specified number of lanes to be used to transmit frames on the SERDES link 110. For example, assuming an embodiment that uses a single threshold, N, a predetermined number of lanes, M, can be used for transmitting frames when bandwidth demand is at or above N, while a second predetermined number of lanes, K, can be used for transmitting frames when bandwidth demand is below N. More specifically, in an embodiment that includes 16 lanes and has a single threshold set at 50% of typical link bandwidth, 16 lanes can be used to transmit frames when bandwidth demand is at or above 50% of typical bandwidth, while 12, 10, 8, 4, 2, or 1 lane can be used to transfer data when bandwidth demands are below 50%.” [0086], “assuming an embodiment that includes 16 lanes in a SERDES link, 8 lanes, 4 lanes, or 2 lanes can be used, which causes the frames to be sent in two clock cycles (i.e., in 24 ticks for a TX 204 that can send 12 cells on a lane per clock cycle), four clock cycles, or eight clock cycles, respectively.”
Claims 2, 8, and 15 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12235712 in view of Kapil et al. (US 20100316065).
Although the claims at issue are not identical, they are not patentably distinct from each other because claims 2, 8, and 15 of the instant application is obvious by patent claim 1 of US 12235712 and in view of Kapil et al. (US 20100316065) in that the patent claims contain all the limitations of the instant application.
US 12235712 and Kapil are analogous art. Kapil is cited to teach a common signaling rate used for both bandwidth modes. Based on Kapil, it would have been obvious at the time the invention was invented to a person having ordinary skill in the art to which said subject matter pertains to have modified US 12235712 to use a sane signaling rate used for both bandwidth modes. Furthermore, being able to maintain a same signaling rate used for both bandwidth modes improves on US 12235712 by being able to maintain calibration not changing the clock rate with different bandwidths. To one of ordinary skill in the art at the time the invention was filed would it would have been advantageous to make this modification because it improves overall system performance by being able to maintain calibration of the bus.
Instant Application
US 12235712
Kapil et al.
Claim 8: A first integrated circuit, comprising: a plurality of link interfaces, at least one of the plurality of link interfaces to receive, from a second integrated circuit, a first bandwidth mode indicator via a first control packet, and a second bandwidth mode indicator via a second control packet;
Claim 2: A memory controller, comprising: a plurality of control transmitter circuits to transmit, to a memory device, control information including first control information associated with a first mode of the memory controller, second control information associated with a second mode of the memory controller,
and mode circuitry to, based on the first bandwidth mode indicator, operate the plurality of link interfaces in a first bandwidth mode that transfers data via each of the plurality of link interfaces,
based on the first mode, select between concurrently routing data received from the memory device across all of the plurality of data receiver circuits when all of the plurality of data receiver circuits are enabled and
wherein each link interface of the plurality of link interfaces is to each respectively transfer data at a same signaling rate,
[0063], “each threshold is associated with a specified number of lanes to be used to transmit frames on the SERDES link 110. For example, assuming an embodiment that uses a single threshold, N, a predetermined number of lanes, M, can be used for transmitting frames when bandwidth demand is at or above N, while a second predetermined number of lanes, K, can be used for transmitting frames when bandwidth demand is below N. More specifically, in an embodiment that includes 16 lanes and has a single threshold set at 50% of typical link bandwidth, 16 lanes can be used to transmit frames when bandwidth demand is at or above 50% of typical bandwidth, while 12, 10, 8, 4, 2, or 1 lane can be used to transfer data when bandwidth demands are below 50%.” [0086], “assuming an embodiment that includes 16 lanes in a SERDES link, 8 lanes, 4 lanes, or 2 lanes can be used, which causes the frames to be sent in two clock cycles (i.e., in 24 ticks for a TX 204 that can send 12 cells on a lane per clock cycle), four clock cycles, or eight clock cycles, respectively.”
the mode circuitry also to, based on the second bandwidth mode indicator, operate the plurality of link interfaces in a second bandwidth mode that transfers data via each of a subset of the plurality of link interfaces,
to, based on the second mode, employ at least partial deserialization to concurrently route the data received from the memory device from a first subset of the plurality of data receiver circuits when a second subset of the plurality of data receiver circuits are disabled,
wherein each link interface of the subset of the plurality of link interfaces is to each respectively transfer data at the same signaling rate.
[0063], “each threshold is associated with a specified number of lanes to be used to transmit frames on the SERDES link 110. For example, assuming an embodiment that uses a single threshold, N, a predetermined number of lanes, M, can be used for transmitting frames when bandwidth demand is at or above N, while a second predetermined number of lanes, K, can be used for transmitting frames when bandwidth demand is below N. More specifically, in an embodiment that includes 16 lanes and has a single threshold set at 50% of typical link bandwidth, 16 lanes can be used to transmit frames when bandwidth demand is at or above 50% of typical bandwidth, while 12, 10, 8, 4, 2, or 1 lane can be used to transfer data when bandwidth demands are below 50%.” [0086], “assuming an embodiment that includes 16 lanes in a SERDES link, 8 lanes, 4 lanes, or 2 lanes can be used, which causes the frames to be sent in two clock cycles (i.e., in 24 ticks for a TX 204 that can send 12 cells on a lane per clock cycle), four clock cycles, or eight clock cycles, respectively.”
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(b) the invention was patented or described in a printed publication in this or a foreign country or in public use or on sale in this country, more than one year prior to the date of application for patent in the United States.
Claim(s) 2-3, 6-10, and 17-18 is/are rejected under pre-AIA 35 U.S.C. 102(b) as being anticipated by Kapil et al. (US 20100316065).
Regarding claim 3, Kapil teaches wherein the bandwidth mode indicator is based on bandwidth control information received via at least one of the plurality of link interfaces. (Claim 1, “ determine a second number of lanes to be used to transmit frames on the high-speed link based on a bandwidth demand on the high-speed link; and send an indicator of the second number of lanes to a receiver on the high-speed link; and in response to an acknowledgement of the indicator received from the receiver, transmit subsequent frames on the high-speed link using the second number of lanes from a predetermined frame.”)
Regarding claim 6, Kapil teaches wherein the integrated circuit includes a memory array to store the data. (Fig. 2 (Memory subsystem – 106), [0037], “Memory subsystem 108 can include memory for storing data and/or instructions for processing subsystems 102 and 104. For example, the memory subsystem 108 can include one or more dual inline memory modules (DIMMs) that each include a number of separate dynamic random access memory (DRAM) chips that together comprise a memory for computer system 100.”)
Regarding claim 7, Kapil teaches wherein, based on the bandwidth mode indicator, bandwidth control information is transmitted via at least one of the plurality of link interfaces. (Claim 1, “ determine a second number of lanes to be used to transmit frames on the high-speed link based on a bandwidth demand on the high-speed link; and send an indicator of the second number of lanes to a receiver on the high-speed link; and in response to an acknowledgement of the indicator received from the receiver, transmit subsequent frames on the high-speed link using the second number of lanes from a predetermined frame.”)
Regarding claim 8, Kapil teaches
A first integrated circuit, comprising:
a plurality of link interfaces (Fig. 2 (Serdes links – 110), at least one of the plurality of link interfaces to receive (Fig. 2 (RX – 206)), from a second integrated circuit, a first bandwidth mode indicator via a first control packet, and a second bandwidth mode indicator via a second control packet; and (Figs. 2, 5, and 11, [0046], “The SERDES links 110 include northbound link 200 and southbound link 202 coupled between host 106 and memory subsystem 108. Both memory subsystem 108 and host 106 include a transmitter circuit (TX) 204 that is configured to transmit frames (which contain data and/or commands) on the corresponding SERDES link 110.”, [0066], “TX 204 then sends an indication of a second number of lanes to be used to transmit frames to a receiver (e.g., RX 206) on the SERDES link 110 (step 504). In some embodiments, sending the indication involves including the indication in a next sync frame sent to the receiver on the SERDES link 110. For example, using the thresholds and lane numbers described above, if the bandwidth has increased from 25% to 77%, TX 204 can include an indication in the next sync frame that 12 lanes are to be used to transmit frames on the link.” and Claim 12 “wherein the transmitter circuit is transmitting frames using a first number of lanes, comprising: determining a second number of lanes to be used to transmit frames on the high-speed link based on a bandwidth demand on the high-speed link; sending an indicator of the second number of lanes to a receiver on the high-speed link; and in response to receiving an acknowledgement of the indicator from the receiver, transmitting subsequent frames on the high-speed link using the second number of lanes from a predetermined frame.”)
mode circuitry to, based on the first bandwidth mode indicator, operate the plurality of link interfaces in a first bandwidth mode that transfers data via each of the plurality of link interfaces, wherein each link interface of the plurality of link interfaces is to each respectively transfer data at a same signaling rate, the mode circuitry also to, based on the second bandwidth mode indicator, operate the plurality of link interfaces in a second bandwidth mode that transfers data via each of a subset of the plurality of link interfaces, wherein each link interface of the subset of the plurality of link interfaces is to each respectively transfer data at the same signaling rate. ([0066], “TX 204 then sends an indication of a second number of lanes to be used to transmit frames to a receiver (e.g., RX 206) on the SERDES link 110 (step 504).”, [0070], “ the indication can be an indication that the number of lanes is to be reduced or increased.” [0090], “the SERDES link uses 16 lanes initially, but based on a reduction in bandwidth demand, the transmitter (e.g., TX 204) reduces the number of lanes to eight. If the bandwidth demand on the link remains at the reduced level a first predetermined time (100 ms, 1 s, 1 min., etc.) the transmitter further reduces the number of lanes to four. If the bandwidth demand for the link subsequently remains at the reduced level for a second, and possibly different, predetermined time interval (100 ms, 1 s, 1 min., etc.), the transmitter further reduces the number of lanes to two.” And [0086], “For example, assuming an embodiment that includes 16 lanes in a SERDES link, 8 lanes, 4 lanes, or 2 lanes can be used, which causes the frames to be sent in two clock cycles (i.e., in 24 ticks for a TX 204 that can send 12 cells on a lane per clock cycle), four clock cycles, or eight clock cycles, respectively.” Where the lanes can be changed from 16 to 8 to 4 lanes, etc. via sending an indication on the links, i.e. the indicators changing from a first bandwidth mode to a second bandwidth mode to a third bandwidth mode, etc.)
Regarding claim 9, Kapil teaches wherein respective portions of the first control packet are received via respective ones of all of the subset of the plurality of link interfaces. ([0066], “TX 204 then sends an indication of a second number of lanes to be used to transmit frames to a receiver (e.g., RX 206) on the SERDES link 110 (step 504).”, [0070], “ the indication can be an indication that the number of lanes is to be reduced or increased.” [0090], “the SERDES link uses 16 lanes initially, but based on a reduction in bandwidth demand, the transmitter (e.g., TX 204) reduces the number of lanes to eight. If the bandwidth demand on the link remains at the reduced level a first predetermined time (100 ms, 1 s, 1 min., etc.) the transmitter further reduces the number of lanes to four. If the bandwidth demand for the link subsequently remains at the reduced level for a second, and possibly different, predetermined time interval (100 ms, 1 s, 1 min., etc.), the transmitter further reduces the number of lanes to two.” And [0086], “For example, assuming an embodiment that includes 16 lanes in a SERDES link, 8 lanes, 4 lanes, or 2 lanes can be used”, where the indication (the first control packet) is for all 16 lanes to operate)
Regarding claim 10, Kapil teaches wherein respective portions of the second control packet are received via respective ones of all of the plurality of link interfaces. ([0066], “TX 204 then sends an indication of a second number of lanes to be used to transmit frames to a receiver (e.g., RX 206) on the SERDES link 110 (step 504).”, [0070], “the indication can be an indication that the number of lanes is to be reduced or increased.”)
Regarding claim 13, Kapil teaches wherein at least one of the plurality of link interfaces is to receive, from the second integrated circuit while the plurality of link interfaces are operating in the first bandwidth mode, a third control packet comprising a read command. (Figs. 1-2 and 5, [0040-41], “The SERDES links 110 are used to transmit data and/or commands between host 106 and memory subsystem 108 in the indicated direction. The first of the SERDES links 110 between host 106 and memory subsystem 108 can be referred to as the "downstream" or "southbound" link, on which host 106 transmits data and/or commands to memory subsystem 108. … each SERDES link 110 includes a number of parallel serial channels or "lanes" that are used to transmit data and/or commands on the SERDES links. For example, the some embodiments can include 8, 14, 16, 30, or another number of lanes in each SERDES link 110.”, [0046], “Both memory subsystem 108 and host 106 include a transmitter circuit (TX) 204 that is configured to transmit frames (which contain data and/or commands) on the corresponding SERDES link 110. In addition, memory subsystem 108 and host 106 include a receiver circuit (RX) 206 that is configured to receive frames on the corresponding SERDES link 110.”, [0063], “each threshold is associated with a specified number of lanes to be used to transmit frames on the SERDES link 110. For example, assuming an embodiment that uses a single threshold, N, a predetermined number of lanes, M, can be used for transmitting frames when bandwidth demand is at or above N, while a second predetermined number of lanes, K, can be used for transmitting frames when bandwidth demand is below N. More specifically, in an embodiment that includes 16 lanes and has a single threshold set at 50% of typical link bandwidth, 16 lanes can be used to transmit frames when bandwidth demand is at or above 50% of typical bandwidth, while 12, 10, 8, 4, 2, or 1 lane can be used to transfer data when bandwidth demands are below 50%.” Where the transmitting commands/data when all 16 lanes are enabled is interpreted as including writing and reading data to the memory (i.e. the third control packet is a read command.))
Regarding claim 14, Kapil teaches further comprising a memory array to store the data, wherein, based on the read command, the first integrated circuit is to transfer, to the second integrated circuit and using the plurality of link interfaces, data accessed from the memory array. (Fig. 1-2, 5, and 11, [0037], “Memory subsystem 108 can include memory for storing data and/or instructions for processing subsystems 102 and 104.” [0046], “Both memory subsystem 108 and host 106 include a transmitter circuit (TX) 204 that is configured to transmit frames (which contain data and/or commands) on the corresponding SERDES link 110. In addition, memory subsystem 108 and host 106 include a receiver circuit (RX) 206 that is configured to receive frames on the corresponding SERDES link 110.”, [0090], “As can be seen in FIG. 11, the SERDES link uses 16 lanes initially, but based on a reduction in bandwidth demand, the transmitter (e.g., TX 204) reduces the number of lanes to eight.” Where using 16 lanes is interpreted as using all of the plurality of link interfaces for storing data based on a read command)
Regarding claim 15, Kapil teaches wherein at least one of the subset of the plurality of link interfaces is to receive, from the second integrated circuit while the plurality of link interfaces are operating in the second bandwidth mode, a third control packet comprising a read command. (Figs. 1-2 and 5, [0040-41], “The SERDES links 110 are used to transmit data and/or commands between host 106 and memory subsystem 108 in the indicated direction. The first of the SERDES links 110 between host 106 and memory subsystem 108 can be referred to as the "downstream" or "southbound" link, on which host 106 transmits data and/or commands to memory subsystem 108. … each SERDES link 110 includes a number of parallel serial channels or "lanes" that are used to transmit data and/or commands on the SERDES links. For example, the some embodiments can include 8, 14, 16, 30, or another number of lanes in each SERDES link 110.”, [0046], “Both memory subsystem 108 and host 106 include a transmitter circuit (TX) 204 that is configured to transmit frames (which contain data and/or commands) on the corresponding SERDES link 110. In addition, memory subsystem 108 and host 106 include a receiver circuit (RX) 206 that is configured to receive frames on the corresponding SERDES link 110.”, [0063], “each threshold is associated with a specified number of lanes to be used to transmit frames on the SERDES link 110. For example, assuming an embodiment that uses a single threshold, N, a predetermined number of lanes, M, can be used for transmitting frames when bandwidth demand is at or above N, while a second predetermined number of lanes, K, can be used for transmitting frames when bandwidth demand is below N. More specifically, in an embodiment that includes 16 lanes and has a single threshold set at 50% of typical link bandwidth, 16 lanes can be used to transmit frames when bandwidth demand is at or above 50% of typical bandwidth, while 12, 10, 8, 4, 2, or 1 lane can be used to transfer data when bandwidth demands are below 50%.” Where the transmitting commands/data when some lanes have been placed in a lower power mode (i.e. fewer lanes are enabled for example 8 or 4) is interpreted as including writing and reading data to the memory (i.e. the third control packet is a read command.))
Regarding claim 16, Kapil teaches further comprising a memory array to store the data, wherein, based on the read command, the first integrated circuit is to transfer, to the second integrated circuit and using the subset of the plurality of link interfaces, data accessed from the memory array of the first integrated circuit. (Fig. 1-2, 5, and 11, [0037], “Memory subsystem 108 can include memory for storing data and/or instructions for processing subsystems 102 and 104.” [0046], “Both memory subsystem 108 and host 106 include a transmitter circuit (TX) 204 that is configured to transmit frames (which contain data and/or commands) on the corresponding SERDES link 110. In addition, memory subsystem 108 and host 106 include a receiver circuit (RX) 206 that is configured to receive frames on the corresponding SERDES link 110.”, [0090], “As can be seen in FIG. 11, the SERDES link uses 16 lanes initially, but based on a reduction in bandwidth demand, the transmitter (e.g., TX 204) reduces the number of lanes to eight.” Where after reducing to 8 lanes is interpreted as a subset of the plurality of link interfaces for storing data based on a read command)
Regarding claim 18, Kapil teaches wherein the first control packet and the second control packet are received from a controller integrated circuit device. ([0038-39], “Host 106 can include any device configured to serve as an interface or controller between processing subsystem 104 and memory subsystem 108. For example, in some embodiments host 106 is a memory controller, a buffer, and/or an interface circuit. … These SERDES links 110 are used to transmit data and/or commands between the processing subsystems and host 106”)
As to claims 2 and 17, Kapil teaches these claims according to the reasoning provided in claim 8.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 11, and 19-21 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Kapil in view of Ku et al. (US 8724483).
Regarding claim 11, Kapil does not teach generating calibration information but Ku teaches further comprising: calibration circuitry to generate calibration information to be used to calibrate at least one of the plurality of link interfaces. (Abstract, " implementing a loopback configuration between components of an electronic system, thereby enabling more flexible, efficient and effective calibration and/or testing of the electronic system using a single interface.")
Kapil and Ku are analogous art. Ku is cited to teach a similar concept of
improving performance with buses. Ku specifically teaches generation information to enable a loopback mode for calibration of bus lanes. Based on Ku, it would have been obvious at the time the invention was invented to a person having ordinary skill in the art to which said subject matter pertains to have modified Kapil generate information to use a loopback mode for calibration of bus lanes. Furthermore, being able to use a loopback mode for calibration improves on Kapil by being able to provide an efficient calibration. To one of ordinary skill in the art at the time the invention was filed would it would have been advantageous to make this modification because it "enable[es] more flexible, efficient and effective calibration"., Abstract
Regarding claim 20, Kapil teaches communication of a high speed bus but does not specifically teach using calibration to calibrate the bus. Ku teaches wherein the calibration information is to be provided to the controller integrated circuit device. (col. 7, lines training data may be communicated from graphics processor 150 over partition 282 and used to adjust the delay of a frame buffer clock such that subsequently-transferred data may be clocked out from partition 282 by interface component 265.”)
Kapil and Ku are analogous art. Ku is cited to teach a similar concept of
improving performance with buses. Ku specifically teaches generation information to enable a loopback mode for calibration of bus lanes. Based on Ku, it would have been obvious at the time the invention was invented to a person having ordinary skill in the art to which said subject matter pertains to have modified Kapil generate information to use a loopback mode for calibration of bus lanes. Furthermore, being able to use a loopback mode for calibration improves on Kapil by being able to provide an efficient calibration. To one of ordinary skill in the art at the time the invention was filed would it would have been advantageous to make this modification because it To one of ordinary skill in the art at the time the invention was filed would it would have been advantageous to make this modification because it "enable[es] more flexible, efficient and effective calibration"., Abstract
Regarding claim 21, Kapil teaches sending information on a subset of links of a high speed bus but does not specifically teach sending calibration information on a subset of links. Kapil teaches wherein the calibration information is to be provided to the controller integrated circuit device via the subset of the plurality of transmitter circuits.
Kapil teaches wherein the calibration information is to be provided to the controller integrated circuit device via the subset of the plurality of transmitter circuits.
Kapil and Ku are analogous art. Ku is cited to teach a similar concept of
improving performance with buses. Ku specifically teaches generation information to enable a loopback mode for calibration of bus lanes for efficient calibration. Based on Ku, it would have been obvious at the time the invention was invented to a person having ordinary skill in the art to which said subject matter pertains to have modified Kapil generate information to use a loopback mode for calibration of bus lanes. Furthermore, being able to use a loopback mode for calibration improves on Kapil by being able to provide an efficient calibration. To one of ordinary skill in the art at the time the invention was filed would it would have been advantageous to make this modification because it To one of ordinary skill in the art at the time the invention was filed would it would have been advantageous to make this modification because it "enable[es] more flexible, efficient and effective calibration"., Abstract
As to claims 4 and 19, Kapil and Ku teach these claims according to the reasoning provided in claim 11.
Claim 5 and 12 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Kapil and Ku in view of Iyer et al. (US 20130007491)
Regarding claim 12, Kapil and Ku do not teach but Iyer teaches wherein the calibration circuitry is to generate the calibration information based on at least one of the first bandwidth mode indicator and the second bandwidth mode indicator. ([0021], "The timing diagrams also show the signaling on the idle lanes that allows probes (e.g., electro-magnetic coupler probes) to initialize themselves before the lanes start carrying flits. In an embodiment, this signaling can be used to allow for additional conditioning (e.g., calibration, compensation, etc.) of the idle lanes prior to carrying flits. The timing diagrams further illustrate staggered differential DC tails when lanes enter electrical idle-this may be used to turn off some circuits (including for example equalizers) in a staggered manner.")
Kapil, Ku, and lyer are analogous art. lyer is cited to teach a similar concept of
modifying transmission bandwidths and calibrating lanes. lyer specifically teaches disabling lanes while other lanes remain active/enabled. Based on lyer, it would have been obvious at the time the invention was invented to a person having ordinary skill in the art to which said subject matter pertains to have modified Kapil calibrate lanes in different bandwidth modes. Furthermore, being able to maintain a set of lanes enabled improves on Kapil by being able to retrain and improve efficiency. To one of ordinary skill in the art at the time the invention was filed would it would have been advantageous to make this modification because it “ Some of the embodiments discussed herein may provide for link width modulation that supports probes (e.g., electro-magnetic coupler probes), retraining (e.g., to ensure bit lock maintenance), equalization, and/or improved efficiency.”
As to claim 5, Kapil, Ku, and Iyer teach these claims according to the reasoning provided in claim 12.
Conclusion
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/CHERI L HARRINGTON/Examiner, Art Unit 2176 June 23, 2026
/PHIL K NGUYEN/Primary Examiner, Art Unit 2176
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