Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This office action is in response to communication filed on 01/15/2026. Claims 1 – 20 are pending on this application.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cretu et al. Pub. No. 2022/0407535.
Regarding claim 1. Fig. 2 of Cretu et al. discloses bootstrapped switch circuit (paragraph 0050), comprising: a sample transistor (MS) comprising a gate (gate of Ms) , a source (source of Ms) coupled to an input terminal (Vin)), and a drain (Drain of Ms) coupled to an output terminal (Vout) ; a bootstrap capacitor (CB) ; a charge path (charge phat of M3 to M1) configured to charge the bootstrap capacitor (CB) during a hold phase (CLK); a bootstrap path (path of M4, M2, M7) configured to apply a voltage (Y) of the bootstrap capacitor (CB) to the gate of the sample transistor (gate of Ms) during a sample phase (sampling phase of Ms), the bootstrap path (path of M4, M2, M7) including: a low-side transistor (M2) configured to couple a first terminal (first terminal CB) of the bootstrap capacitor (CB) to the source of the sample transistor (source of Ms) during the sample phase (sample phase of Ms) ; and a high-side transistor (M7) configured to couple a second terminal of the bootstrap capacitor (second terminal of CB) to the gate of the sample transistor (gate of Ms) during the sample phase (sampling phase of Ms); and a bootstrap transistor (M7) having gate (gate of M7) coupled to the gate of the sample transistor (gate of Ms) and a drain (Drain of M7) coupled to a gate of the high-side transistor (gate of M4), the bootstrap transistor (M7) configured to maintain an on- state of the high-side transistor (M4) during the sample phase (sampling phase of Ms) after the high-side transistor (M4) is initially turned on (initial on M4 by gate control) during the sample phase (sampling phase of Ms).
Regarding claim 2. The bootstrapped switch circuit of claim 1, Fig. 2 further discloses wherein the charge path (M3, M1) comprises: a high-side charge transistor (M3) coupled between a high power supply terminal (VDD) and the second terminal of the bootstrap capacitor (second terminal of CB), wherein a gate of the high-side charge transistor (gate of M3) is coupled to the gate of the sample transistor (GATE OF Ms) ; and a low-side charge transistor (M1) coupled between a low power supply terminal (Ground terminal) and the first terminal of the bootstrap capacitor (first terminal of CB), wherein a gate of the low-side charge transistor (gatge of M1) is driven by a hold signal (CLK) to drive the low-side charge transistor (M1) in an on-state (on of M1) during the hold phase (CLK is high M1 is on) and in an off-state (CLK is low M1 is off) during the sample phase (sampling phase of Ms; paragraph 0012 and 0012).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Cretu et al. Pub. No. 2022/0407535 in view of Monangi et al. U.S. patent No. 10,903,843.
Cretue et al. discloses A analog-to-digital converter (paragraph 0017), comprising: a bootstrapped switch circuit (Fig. 2) including: a sample transistor (MS) comprising a gate (gate of Ms) , a source (source of Ms) coupled to an input terminal (Vin)), and a drain (Drain of Ms) coupled to an output terminal (Vout) ; a bootstrap capacitor (CB) ; a charge path (charge phat of M3 to M1) configured to charge the bootstrap capacitor (CB) during a hold phase (CLK); a bootstrap path (path of M4, M2, M7) configured to apply a voltage (Y) of the bootstrap capacitor (CB) to the gate of the sample transistor (gate of Ms) during a sample phase (sampling phase of Ms), the bootstrap path (path of M4, M2, M7) including: a low-side transistor (M2) configured to couple a first terminal (first terminal CB) of the bootstrap capacitor (CB) to the source of the sample transistor (source of Ms) during the sample phase (sample phase of Ms) ; and a high-side transistor (M7) configured to couple a second terminal of the bootstrap capacitor (second terminal of CB) to the gate of the sample transistor (gate of Ms) during the sample phase (sampling phase of Ms); and a bootstrap transistor (M7) having gate (gate of M7) coupled to the gate of the sample transistor (gate of Ms) and a drain (Drain of M7) coupled to a gate of the high-side transistor (gate of M4), the bootstrap transistor (M7) configured to maintain an on- state of the high-side transistor (M4) during the sample phase (sampling phase of Ms) after the high-side transistor (M4) is initially turned on (initial on M4 by gate control) during the sample phase (sampling phase of Ms).
However, the ADC of Cretue et al. do not discloses: a capacitive digital-to-analog converter (DAC) configured to receive an input signal via the bootstrapped switch circuit during the sample phase and to receive a digital feedback signal during the hold phase; a comparator coupled to the DAC and configured to generate a comparison signal based on a DAC output; and a successive-approximation register (SAR) logic coupled to receive the comparison signal and to provide the digital feedback signal to the capacitive DAC.
Fig. 1 of Monangi et al. disclose an SAR ADC 10.
Fig. 2 of Monangi et al. discloses a Switch capacitor 210 of DAC 110 in Fig. 1.
Fig. 7 of Monangi et al. discloses a bootstrap switching circuit for SAR ADC in Fig. 2.
Fig. 1 of Monagi et al. discloses an SAR ADC (100) comprising: a capacitive digital-to-analog converter (110; see Fig. 2) configured to receive an input signal (Vin) via a bootstrapped switch circuit (105; see Fig. 7) during a sample phase (sampling of Vin) and to receive a digital feedback signal (Dout feedback) during the hold phase (Col. 3 lines4-10); a comparator (115) coupled to the DAC (110) and configured to generate a comparison signal (output of of 115) based on a DAC output (Vdaco); and a successive-approximation register (SAR) logic (120) coupled to receive the comparison signal (output of 115) and to provide the digital feedback signal (Dout feedback) to the capacitive DAC (115).
Cretue et al. and Monagi et al. are common subject matter of bootstrapping switch for ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate SAR ADC of Monagi et al. into ADC of Cretue et al. for the purpose of providing a n improved approach to reduce the power demands of the input amplifier of the ADC is to scale the sampling capacitors depending on the desired implementation. Some designs may require a high-resolution while some designs may use a low-resolution ADC (Col. 4 line 66 to Col. 4 lines 4 of Monagi et al.).
Allowable Subject Matter
7. Claims 3 and 4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art does not teach: wherein the charge path further comprises a charge-path dummy transistor having a drain and a source coupled to a drain of the low-side charge transistor, the charge-path dummy transistor further having a gate driven by a sample signal having an opposite phase relative to the hold signal.
8. Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art does not teach: an auxiliary circuit including: an auxiliary capacitor having a first terminal coupled to the first terminal of the bootstrap capacitor; and an auxiliary transistor coupled between a second terminal of the auxiliary capacitor and the high power supply terminal, wherein a gate of the auxiliary transistor is coupled to the gate of the sample transistor; and wherein a body terminal of the high-side transistor, a body terminal of the high-side charge transistor, and a body terminal of the auxiliary transistor, are coupled to the second terminal of the auxiliary capacitor.
9. Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art does not teach: an auxiliary circuit including: an auxiliary capacitor having a first terminal coupled to the first terminal of the bootstrap capacitor; and an auxiliary transistor coupled between a second terminal of the auxiliary capacitor and a high power supply terminal, wherein a gate of the auxiliary transistor is coupled to the gate of the sample transistor; and wherein a body terminal of the high-side transistor and a body terminal of the auxiliary transistor are coupled to the second terminal of the auxiliary capacitor.
10. Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art does not teach: a high-side drive circuit including: a first high-side drive transistor coupled between a high power supply terminal and the gate of the high-side transistor; and a second high-side drive transistor coupled between the gate of the high-side transistor the first terminal of the bootstrap capacitor; and wherein a gate of the first high-side drive transistor is driven by a sample signal to drive the first high-side drive transistor in an off-state during the sample phase and in an on-state during the hold phase; and wherein a gate of the second high-side drive transistor is driven by a tracking signal to drive the second high-side drive transistor in an on-state during an initial portion of the sample phase and to drive the second high-side drive transistor in an off-state during a remaining portion of the sample phase and further during the hold phase.
11. Claim 8-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art does not teach: a low-side drive circuit including: a first low-side drive transistor coupled between the second terminal of the bootstrap capacitor and a gate of the low-side transistor, wherein a gate of the first low-side drive transistor is coupled to the gate of the high-side transistor; and a second low-side drive transistor coupled between the gate of the low-side transistor and a low power supply terminal, wherein a gate of the second low-side drive transistor is driven by a hold signal to drive the second low-side drive transistor in an on-state during the hold phase and in an off-state during the sample phase.
12. Claims 11-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art does not teach: a reset path including: a reset transistor coupled between the gate of the sample transistor and a low power supply terminal, wherein a gate of the reset transistor is driven by a hold signal to drive the reset transistor in an on-state during the hold phase and in an off-state during the sample phase; and a reset dummy transistor having a drain and a source coupled together and to the drain of reset transistor, the reset dummy transistor further having a gate driven by a sample signal having an opposite phase relative to the hold signal.
13. Claim 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art does not teach: an auxiliary circuit including: an auxiliary capacitor having a first terminal coupled to the first terminal of the bootstrap capacitor; and an auxiliary transistor coupled between a second terminal of the auxiliary capacitor and a high power supply terminal, wherein a gate of the auxiliary transistor is coupled to the gate of the sample transistor; and wherein a body terminal of the high-side transistor and a body terminal of the auxiliary transistor are coupled to the second terminal of the auxiliary capacitor.
14. Claim 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art does not teach: a high-side drive circuit including: a first high-side drive transistor coupled between a high power supply terminal and the gate of the high-side transistor; and a second high-side drive transistor coupled between the gate of the high-side transistor the first terminal of the bootstrap capacitor; and wherein a gate of the first high-side drive transistor is driven by a sample signal to drive the first high-side drive transistor in an off-state during the sample phase and in an on-state during the hold phase; and wherein a gate of the second high-side drive transistor is driven by a tracking signal to drive the second high-side drive transistor in an on-state during an initial portion of the sample phase and to drive the second high-side drive transistor in an off-state during a remaining portion of the sample phase and further during the hold phase.
15. Claim 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art does not teach : a first low-side drive transistor coupled between the second terminal of the bootstrap capacitor and a gate of the low-side transistor, wherein a gate of the first low-side drive transistor is coupled to the gate of the high-side transistor; and a second low-side drive transistor coupled between the gate of the low-side transistor and a low power supply terminal, wherein a gate of the second low-side drive transistor is driven by a hold signal to drive the second low-side drive transistor in an on-state during the hold phase and in an off-state during the sample phase.
16. Claims 13-16 are allowed.
The following is an examiner’s statement of reasons for allowance:
With respect to claim 13, in addition to other elements in the claim, prior art considered individual or combination does not teach: a high-side drive circuit including: a first high-side drive transistor coupled between a high power supply terminal and the gate of the high-side transistor; and a second high-side drive transistor coupled between the gate of the high- side transistor the first terminal of the bootstrap capacitor; and wherein a gate of the first high-side drive transistor is driven by the sample signal to drive the first high-side drive transistor in an off-state during the sample phase and in an on-state during the hold phase; and wherein a gate of the second high-side drive transistor is driven by the tracking signal to drive the second high-side drive transistor in an on-state during an initial portion of the sample phase and to drive the second high-side drive transistor in an off-state during a remaining portion of the sample phase and further during the hold phase.
Contact Information
17. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
08/10/2026
/LINH V NGUYEN/Primary Examiner, Art Unit 2845
Prosecution Insights