DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 – 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are:
In claim 1, the pre-amble introduces certain device elements/limitations to lay out the foundation for the method steps which follow in order to perform bit line initializations in Phase Change Memory device. More specifically, “a pair of additional control word lines” were included as part of the memory device structure, but lacks essential cooperative relationships of elements in order to enable one of ORDINARY skill in the art, to “polarize these word lines to reading voltage”. According to the claim, unlike the “plurality of cells being arranged in bit lines and word lines” which has well-understood meaning in the art, the “pair of additional control word lines” need to include further essential structural cooperative relationships of elements to amount to the gap between the necessary structural connections, in order to establish the solid device foundation upon which the method steps make sense. In other words, merely claiming the ”pair of additional control word lines” and then further claiming, in lines 10 – 11, “via the pair of additional control word lines” is not clear how it can attribute to effect the bit line initialization method for the Phase Change memory device.
Claims 2 – 15 are also rejected for being dependent from base claim 1.
Appropriate corrections/clarifications are required in order to overcome this type of rejection.
Claims 1 – 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential steps, such omission amounting to a gap between the steps. See MPEP § 2172.01. The omitted steps are:
Again in claim 1, without structural connectivity between the pair of additional control word lines to the memory structure, it’s not clear how the step of “clamping the bit lines at the threshold voltage via the pair of additional control word lines” effect the method of performing bit line initialization in order to enable ONE OF ORDINARY Skill in the art in to make use of the invention.
Claims 2 – 15 are also rejected for being dependent from base claim 1.
Appropriate corrections/clarifications are required in order to overcome this type of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 – 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Resta et al. (US Pat pub 2005/0185572) in view of Bolandrina et al. (US Pat Pub 2015/0213888), and further in view of Ruta et al. (US Pat Pub 2023/0130268).
Regarding claims 1, 14 and 15, Resta et al. discloses a method (see in particular paragraphs [0022]-[0036], figures 1-4, and the advantages provided as disclosed in paragraph [0037]) a method of performing bit line initializations (figures 1, 4: see initial bit line control by charge control circuit 8) in a Phase Change Memory, PCM device (figures 1-4), the PCM device comprising: a plurality of cells (PCM cells 3) selectable via a plurality of respective transistors (BJT/PNP bipolar selection transistors 15), preferably bipolar transistors, said plurality of cells being arranged in bit lines (12) and word lines (13), and a pair of additional control word lines (see figure 4 with control lines connected to gate terminals of charge control transistors 32, each such transistor being connected to a respective bit line), wherein the method comprises:
polarizing the bit lines (12) to a polarization voltage (Vx), said polarization voltage being higher than a threshold voltage (Vτ₀) of the plurality of respective transistors (figure 4, paragraph [0036]: equations (4)-(6) with Vₓ=VINT+VTQ);
clamping said bit lines (12) at said voltage (Vx) via said pair of additional control line (note that the claims’ use of terminology “control word lines” does NOT mean the well-understood “word line” in the memory art. Here, they are voltage control lines according to the specification, and therefore will be interpreted as such); and
polarizing the word lines (13) to a reading voltage (paragraph [0034]: during read a deselect bias voltage VSB of 3.6 V is applied to deselected word lines), said reading voltage being higher than the polarization voltage (Vₓ with Vₓ < 3 V).
While Resta et al. did not clearly disclose the control lines connected to the gate terminals of the bit line charge control transistors 32, i.e. by defining that such control lines are provided by a pair of additional word lines, whereas D1 does not specify such control line implementation using word lines. The provision of control signal lines for a memory array using word lines has however to be considered as an obvious option for the skilled person in the field of semiconductor memory design, no inventive skill can be attributed to such memory control line implementation: also see for example bit line clamping realizations by even/odd word lines WL_CLAMP in Bolandrina et al., figure 5, paragraphs [0040]-[0041] or bit line clamping to the base-emitter voltage VBE of the bipolar clamping transistors 110 using word line WLCLAMP in Ruta et al., figure 1, paragraphs [0034], [0040].
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to combine the references as cited above, so that neighbor memory cell disturbance may be reduced (see Bolandrina et al. para 0029 and 0030).
Claim(s) 2 – 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Resta et al. (US Pat pub 2005/0185572) in view of Bolandrina et al. (US Pat Pub 2015/0213888), and further in view of Ruta et al. (US Pat Pub 2023/0130268) as well as Morgan et al. (US Pat 5,883,827).
Claims 2 – 13 do not appear to contain any additional features which in combination with the features of any claim(s) to which they refer, meet the requirements with respect to novelty and inventive step, since their additional features are either directly disclosed in D1 or obvious to the skilled person because concerning modifications in the phase change memory circuit architecture or operation, these modifications however coming within the scope of the customary practice followed by the skilled person, especially as the advantages thus achieved can be readily contemplated in advance. In particular
regarding claim 2 (see fast initial reading method steps, Resta et al., paragraphs [0013], [0036], [0037]; Ruta et al., paragraph [0040]);
Regarding claims 3 – 11: their subject-matter are considered obvious circuit operation and design options, see for example plurality of pass transistors 272 - 275 to main line 62 in Morgan et al., figure 2, column 4, line 10 - column 8, line 55; and
With respect to claims 12 and 13: similarly their subject-matter are considered obvious circuit design options for the realization of word line biasing/polarization means.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to realize the claimed features generically and additionally claimed in claims 2 – 13, in order to operate the initializations in the Phase Change Memory device efficiently.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LY D PHAM whose telephone number is (571)272-1793. The examiner can normally be reached M-F: 8am-5pm.
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LY D. PHAM
Examiner
Art Unit 2827
/LY D PHAM/Primary Examiner, Art Unit 2827 September 1, 2026
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