DETAILED ACTION
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 6 and 16-20 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim(s) 6 recite(s) the language (emphasis added) “the second IC die is stacked onto the third IC die, and coupled to the third IC die via microbumps”, where “microbumps” is already recited in claim 1 and it is unclear if the two limitations are the same.
Claim(s) 16 recite(s) the language (emphasis added) “ones of the plurality of first IC dies are coupled, using microbumps, to at least one adjacent first IC die of the stack; and a second IC die coupled via microbumps to a base one of the plurality of first IC dies”, where it is unclear if the two recitations of “microbumps” are the same.
Claim(s) 20 recite(s) the language (emphasis added) “coupled to the particular physical layer circuit via microbumps coupled to a bottom of the second IC die”, where it is unclear if the “microbumps” of claim 20 are the same the the “microbumps” recited in claim 16.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 16, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park, US 20140146589 A1, in view of Smith, US 9432298 B1.
As to claim 1, Park discloses a system (see Park Fig 1) comprising:
a stack of integrated circuit (IC) dies (see Park Fig 12 Refs 530, 540, and 550, and Para [0157]), wherein
ones of the stack of IC dies include (see Park Fig 4): a plurality of first dies IC (see Park Fig 4 Ref DRAM, Fig 1 Ref 100, and Para [0086]) that include a first type of dynamic random access memory (DRAM) (see Park Fig 1 Ref 100), wherein
ones of the plurality of first IC dies (see Park Fig 4 Ref DRAM and Para [0086]) are coupled to at least one adjacent first IC die of the stack (see Park Fig 12 Refs 530, 540, and 550); and a second IC die (see Park Fig 4 Ref DRAM Cache, Fig 1 Ref 110, and Para [0086] and Fig 12 Ref 520) coupled to a base one of the plurality of first IC dies (see Park Fig 4 bottom of Ref 200), wherein
the second IC die includes: a second type of DRAM (see Park Fig 4 Ref DRAM Cache); and a particular physical layer circuit that is configured to communicate with the first type of DRAM in the stack of first IC dies (see Park Fig 12 Ref 510).
Park does not appear to explicitly disclose coupled, via microbumps.
Smith discloses coupled, via microbumps (see Smith Fig 4 Ref Solder Bump).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a system, as disclosed by Park, may be wired together with particular interconnects, as disclosed by Smith. The inventions are well known variants of vertically stacked memory devices, and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Smith’s attempt to simplified device manufacture (see Smith Col 26 Lines 1-9).
As to claim 16, Park and Smith disclose a stacked memory device (see Park Fig 12) comprising:
a plurality of first integrated circuit (IC) dies (see Park Fig 12 Refs 530, 540, and 550), arranged in a stack (see Park Fig 12), wherein
the plurality of first IC dies includes a first type of dynamic random access memory (DRAM) (see Park Fig 4 Ref DRAM, Fig 1 Ref 100, and Para [0086]), and wherein
ones of the plurality of first IC dies are coupled, using microbumps (see Smith Fig 4 Ref Solder Bump), to at least one adjacent first IC die of the stack (see Park Fig 12 Refs 520, 530, 540, and 550); and
a second IC die (see Park Fig 4 Ref DRAM Cache, Fig 1 Ref 110, and Para [0086] and Fig 12 Ref 520) coupled via microbumps (see Park Fig 4 Ref B40) to a base one of the plurality of first IC dies (see Park Fig 4 bottom of Ref 200), wherein
the second IC die includes: a second type of DRAM (see Park Fig 4 Ref DRAM Cache); and a particular physical layer circuit (see Park Fig 12 Ref 51) configured to communicate with the first type of DRAM in the stack of first IC dies and the second type of DRAM in the second IC die (see Park Fig 12 Ref 510).
As to claim 17, Park and Smith disclose the stacked memory device of claim 16, further comprising
a connection layer (see Park Fig 4 Ref 300) including: a first plurality of microbumps (see Park Fig 4 Ref B40; Coupled does not imply directly coupled.) coupled to the particular physical layer circuit in the second IC die (see Park Fig 12 Ref 520); and a second plurality of microbumps (see Park Fig 4 Ref B20) coupled to the first plurality of microbumps.
Allowable Subject Matter
Claims 10-15 are allowed.
Claims 2-5 and 7-9 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 18-20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not appear to disclose (as recited in claim 2):
the second IC die further includes a different physical layer circuit that is configured to communicate with the second type of DRAM.
The prior art does not appear to disclose (as recited in claim 5):
a third IC die coupled to the second IC die, wherein the third IC die includes: a different physical layer circuit that is configured to communicate with the particular physical layer circuit.
The prior art does not appear to disclose (as recited in claim 10):
accessing, by a first physical layer circuit on a second integrated circuit (IC) die, a plurality of first memory circuits of a first type of dynamic random access memory (DRAM), wherein the plurality of first memory circuits is included on a plurality of first IC dies; and accessing, by a second physical layer circuit on the second IC die, a second memory circuit of a second type of DRAM.
The prior art does not appear to disclose (as recited in claim 18):
a third IC die coupled to the connection layer via the second plurality of microbumps; wherein the third IC die includes: a different physical layer circuit that is coupled to the particular physical layer circuit via the second plurality of microbumps.
The prior art does not appear to disclose (as recited in claim 20):
a third IC die that includes: a different physical layer circuit that is coupled to the particular physical layer circuit via microbumps coupled to a bottom of the second IC die.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEROME LARRY LEBOEUF whose telephone number is (571)272-7612. The examiner can normally be reached M-Th: 8:00AM - 6:00PM EST.
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/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 09/01/2026
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