DETAILED ACTION
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 7 of U.S. Patent No. 10916290 B2 in view of Thottethodi, US 20150357306 A1.
Examiner acknowledges the restriction requirement filed 04/23/2019 for Application Number 16/098916, the parent case of both the at issue claim and US 10916290 B2. The scope of claim and the claims 1 and 7 of US 10916290 B2 are generic to the restriction between species filed 04/23/2019, more specifically generic between figures 12 and 14, and a double patenting rejection claim 1 in view of US 10916290 B2 is proper.
Claims 1 and 7 of US 10916290 B2 recite substantially the same device as claim 1, but do not explicitly disclose the memory form as die stacked ICs coupled to a base. Thottethodi discloses die stacked ICs coupled to a base (see Thottethodi Para [0013] and Fig 2).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a system, as disclosed by US 10916290 B2, may be implemented in die stacks, as disclosed by Thottethodi. The inventions are well known variants of stacked memory structures, and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Thottethodi’s attempt to improve processing efficiency (see Thottethodi Para [0013]).
Allowable Subject Matter
Claims 10-20 are allowed.
Claims 1-9 would be allowable if rewritten or amended to overcome the double patenting rejection set forth in this Office action, or a terminal disclaimer is filed.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not appear to disclose (as recited in claim 1):
a second IC die coupled to a base one of the plurality of first IC dies, wherein
the second IC die includes: a second type of DRAM with a second memory array that is less dense than a first memory array in the first type of DRAM; and
a first physical layer circuit that is configured to communicate with the stack of first IC dies.
The prior art does not appear to disclose (as recited in claim 10):
the second memory array is included on a second IC die that is coupled to a base one of the plurality of first IC dies, wherein the second memory array is less dense than ones of the plurality of first memory arrays; and wherein the first physical layer circuit is included on the second IC die.
The prior art does not appear to disclose (as recited in claim 17):
the second IC die includes: a second type of DRAM with a second memory array that is less dense than a first memory array in the first type of DRAM; a first physical layer circuit that is configured to communicate with the stack of first IC dies; and
a second physical layer circuit coupled to pins located on a bottom of the second IC die.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEROME LARRY LEBOEUF whose telephone number is (571)272-7612. The examiner can normally be reached M-Th: 8:00AM - 6:00PM EST.
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/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 07/14/2026
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