DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, or 365(c) is acknowledged. In addition, acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 19/022,491, filed on January 15, 2025.
Oath/Declaration
Oath/Declaration as filed on January 15, 2025 is noted by the Examiner.
Claim Objections
Claim 1 is objected to because of the following informalities:
The claim recites limitations “the scan signals” in twelfth and fifteenth lines of the claim, but the limitations are indefinite, because it is unclear as to which one of the scan signals of a first operating frequency or scan signals of a second operating frequency recited in eighth thru tenth lines of the claim are being referred to. Therefore, Examiner suggests the limitations should be amended, without adding new matter, in a manner that resolves the indefiniteness issue. Accordingly, any claims dependent on claim 1 are objected to based on same above reasoning.
Claim 5 is objected to because of the following informalities:
The claim recites limitation “the controller outputs the voltage control signal outputs the clock signal” in fourth thru fifth lines of the claim, but the limitation is indefinite, because it is unclear as to exactly what outputs the clock signal. Therefore, Examiner suggests the limitations should be amended, without adding new matter, in a manner that resolves the indefiniteness issue.
Claim 8 is objected to because of the following informalities:
The claim recites limitations “the scan signals” in fifteenth and eighteenth lines of the claim, but the limitation are indefinite, because it is unclear as to which one of the scan signals of a first operating frequency or scan signals of a second operating frequency recited in eleventh thru thirteenth lines of the claim are being referred to. Therefore, Examiner suggests the limitations should be amended, without adding new matter, in a manner that resolves the indefiniteness issue. Accordingly, any claims dependent on claim 8 are objected to based on same above reasoning.
The claim recites limitation “a signal that swing” in twenty-first line of the claim. The Examiner suggests replacing the word “swing” with “swings” in the limitation to provide further clarity to the claim. Accordingly, any claims dependent on claim 12 are objected to based on same above reasoning.
Claim 15 is objected to because of the following informalities:
The claim recites limitations “the scan signals” in sixteenth and nineteenth lines of the claim, but the limitations are indefinite, because it is unclear as to which one of the scan signals of a first operating frequency or scan signals of a second operating frequency recited in twelfth thru fourteenth lines of the claim are being referred to. Therefore, Examiner suggests the limitations should be amended, without adding new matter, in a manner that resolves the indefiniteness issue. Accordingly, any claims dependent on claim 15 are objected to based on same above reasoning.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claim 1, and 2-7 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1, 2-5, and 8-9 of U.S. Patent No. 11,798,463. Although the claims at issue are not identical, they are not patentably distinct from each other because the scope of the independent claims, mentioned above, are substantially the same.
The following is an example for comparing claim 1 of this application and respective claim 1 of U.S. Patent No. 11,798,463:
Instant Application
U.S. Patent No.
11,798,463
Claim 1
Claim 1
A display device comprising: a display panel including a plurality of first scan lines corresponding to a first display area and a plurality of second scan lines corresponding to a second display area; a scan driving circuit, which drives the plurality of first scan lines and the plurality of second scan lines in synchronization with a clock signal; and a driving controller, which outputs the clock signal, wherein the scan driving circuit provides scan signals of a first operating frequency to the plurality of first scan lines and provides scan signals of a second operating frequency lower than the first operating frequency to the plurality of second scan lines,
A display device comprising:
a display panel including a plurality of pixels connected to a plurality of scan lines; a scan driving circuit, which drives the plurality of scan lines in synchronization with clock signals; and
a driving controller, which outputs the clock signals that include a first clock signal and a second clock signal, wherein, while an operating mode is a multi-frequency mode, the driving controller comparts the display panel into a first display area and a second display area, wherein, in the multi-frequency mode, the scan driving circuit provides scan signals of a first operating frequency to first scan lines positioned in the first display area among the plurality of scan lines, and provides scan signals of a second operating frequency lower than the first operating frequency to second scan lines positioned in the second display area among the plurality of scan lines, wherein a hold frame of the multi-frequency mode includes a first section during which the first display area is driven, and a second section during which the second display area is driven, and
wherein, while the scan driving circuit provides the scan signals to the plurality of first scan lines, the driving controller outputs the clock signal in a normal power mode, and wherein, while the scan driving circuit provides the scan signals to the plurality of second scan lines, the driving controller outputs the clock signal in a low- power mode.
wherein the driving controller has a control signal generator that outputs the first clock signal and the second clock signal in a normal power mode during the first section and outputs the first clock signal and the second clock signal in a low-power mode during the second section.
Independent claim 1 of the instant application teaches “A display device comprising: a display panel including a plurality of first scan lines corresponding to a first display area and a plurality of second scan lines corresponding to a second display area; a scan driving circuit, which drives the plurality of first scan lines and the plurality of second scan lines in synchronization with a clock signal; and a driving controller, which outputs the clock signal, wherein the scan driving circuit provides scan signals of a first operating frequency to the plurality of first scan lines and provides scan signals of a second operating frequency lower than the first operating frequency to the plurality of second scan lines, wherein, while the scan driving circuit provides the scan signals to the plurality of first scan lines, the driving controller outputs the clock signal in a normal power mode, and wherein, while the scan driving circuit provides the scan signals to the plurality of second scan lines, the driving controller outputs the clock signal in a low-power mode.” In addition, it would have been obvious to one of ordinary skill in the art to remove the further limitations “a plurality of pixels connected to; signals that include a first clock signal and a second clock signal,; wherein, in the multi-frequency mode,; wherein a hold frame of the multi-frequency mode includes a first section during which the first display area is driven, and a second section during which the second display area is driven”, since omitting the further limitations does not prevent the device from functioning properly, and the claim is in “comprising” format indicating other elements could be added. Moreover, any claims dependent on claim 1 in corresponding grounds of rejection are rejected based at least on same above reasoning.
Claim 8, 9-10, and 12-13 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 12, 13-15, and 18 of U.S. Patent No. 11,798,463. Although the claims at issue are not identical, they are not patentably distinct from each other because the scope of the independent claims, mentioned above, are substantially the same.
The following is an example for comparing claim 8 of this application and respective claim 12 of U.S. Patent No. 11,798,463:
Instant Application
U.S. Patent No.
11,798,463
Claim 8
Claim 12
A display device comprising: a display panel including a plurality of first scan lines corresponding to a first display area and a plurality of second scan lines corresponding to a second display area; a scan driving circuit, which drives the plurality of first scan lines and the plurality of second scan lines in synchronization with a clock signal; a voltage generator, which generates a first voltage and a second voltage in response to a voltage control signal; and a driving controller, which outputs the clock signal and the voltage control signal,
A display device comprising:
a display panel including a plurality of pixels connected to a plurality of scan lines; a scan driving circuit, which drives the plurality of scan lines in synchronization with clock signals;
a voltage generator, which generates a first voltage and a second voltage in response to a voltage control signal; and a driving controller, which outputs the clock signals that include a first clock signal and a second clock signal and the voltage control signal,
wherein, while an operating mode is a multi-frequency mode, the driving controller comparts the display panel into a first display area and a second display area, wherein, in the multi-frequency mode,
wherein the scan driving circuit provides scan signals of a first operating frequency to the plurality of first scan lines and provides scan signals of a second operating frequency lower than the first operating frequency to the plurality of second scan lines, wherein, while the scan driving circuit provides the scan signals to the plurality of first scan lines, a voltage difference between the first voltage and the second voltage is a first value, wherein, while the scan driving circuit provides the scan signals to the plurality of second scan lines, a voltage difference between the first voltage and the second voltage is a second value smaller than the first value, and wherein the clock signal is a signal that swing between the first voltage and the second voltage.
the scan driving circuit provides scan signals of a first operating frequency to first scan lines positioned in the first display area among the plurality of scan lines, and provides scan signals of a second operating frequency lower than the first operating frequency to second scan lines positioned in the second display area among the plurality of scan lines,
wherein a hold frame of the multi-frequency mode includes a first section during which the first display area is driven, and a second section during which the second display area is driven, wherein a voltage difference between the first voltage and the second voltage during the second section is smaller than a voltage difference between the first voltage and the second voltage during the first section, and wherein the clock signals are signals that swing between the first voltage and the second voltage.
Independent claim 8 of the instant application teaches “A display device comprising: a display panel including a plurality of first scan lines corresponding to a first display area and a plurality of second scan lines corresponding to a second display area; a scan driving circuit, which drives the plurality of first scan lines and the plurality of second scan lines in synchronization with a clock signal; a voltage generator, which generates a first voltage and a second voltage in response to a voltage control signal; and a driving controller, which outputs the clock signal and the voltage control signal, wherein the scan driving circuit provides scan signals of a first operating frequency to the plurality of first scan lines and provides scan signals of a second operating frequency lower than the first operating frequency to the plurality of second scan lines, wherein, while the scan driving circuit provides the scan signals to the plurality of first scan lines, a voltage difference between the first voltage and the second voltage is a first value, wherein, while the scan driving circuit provides the scan signals to the plurality of second scan lines, a voltage difference between the first voltage and the second voltage is a second value smaller than the first value, and wherein the clock signal is a signal that swing between the first voltage and the second voltage.” In addition, it would have been obvious to one of ordinary skill in the art to remove the further limitations “signals that include a first clock signal and a second clock signal; wherein, in the multi-frequency mode,; wherein a hold frame of the multi-frequency mode includes a first section during which the first display area is driven, and a second section during which the second display area is driven,”, since omitting the further limitation does not prevent the device from functioning properly, and the claim is in “comprising” format indicating other elements could be added. Moreover, any claims dependent on claim 8 in corresponding grounds of rejection are rejected based at least on same above reasoning.
Claim 15, and 16-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1, 2-4, and 8-9, respectively of U.S. Patent No. 11,798,463 in view of Noh et al., U.S. Patent Application Publication 2021/0174716 A1 (hereinafter Noh). Although the claims at issue are not identical, they are not patentably distinct from each other because the scope of the independent claims, mentioned above, are substantially the same.
The following is an example for comparing claim 15 of this application and respective claim 1 of U.S. Patent No. 11,798,463:
Instant Application
U.S. Patent No.
11,798,463
Claim 15
Claim 1
An electronic device comprising: a display device, which receives a mode signal from a host processor and displays an image, wherein the display device comprises: a display panel including a plurality of first scan lines corresponding to a first display area and a plurality of second scan lines corresponding to a second display area; a scan driving circuit, which drives the plurality of first scan lines and the plurality of second scan lines in synchronization with a clock signal; and a driving controller, which outputs the clock signal in response to the mode signal,
A display device comprising:
a display panel including a plurality of pixels connected to a plurality of scan lines; a scan driving circuit, which drives the plurality of scan lines in synchronization with clock signals; and
a driving controller, which outputs the clock signals that include a first clock signal and a second clock signal, wherein, while an operating mode is a multi-frequency mode, the driving controller comparts the display panel into a first display area and a second display area, wherein, in the multi-frequency mode,
wherein the scan driving circuit provides scan signals of a first operating frequency to the plurality of first scan lines and provides scan signals of a second operating frequency lower than the first operating frequency to the plurality of second scan lines, wherein, while the scan driving circuit provides the scan signals to the plurality of first scan lines, the driving controller outputs the clock signal in a normal power mode, and wherein, while the scan driving circuit provides the scan signals to the plurality of second scan lines, the driving controller outputs the clock signal in a low-power mode.
the scan driving circuit provides scan signals of a first operating frequency to first scan lines positioned in the first display area among the plurality of scan lines, and provides scan signals of a second operating frequency lower than the first operating frequency to second scan lines positioned in the second display area among the plurality of scan lines, wherein a hold frame of the multi-frequency mode includes a first section during which the first display area is driven, and a second section during which the second display area is driven, and wherein the driving controller has a control signal generator that outputs the first clock signal and the second clock signal in a normal power mode during the first section and outputs the first clock signal and the second clock signal in a low-power mode during the second section.
Independent claim 15 of the instant application teaches “An electronic device comprising: a display device, which receives a mode signal from a host processor and displays an image, wherein the display device comprises: a display panel including a plurality of first scan lines corresponding to a first display area and a plurality of second scan lines corresponding to a second display area; a scan driving circuit, which drives the plurality of first scan lines and the plurality of second scan lines in synchronization with a clock signal; and a driving controller, which outputs the clock signal in response to the mode signal, wherein the scan driving circuit provides scan signals of a first operating frequency to the plurality of first scan lines and provides scan signals of a second operating frequency lower than the first operating frequency to the plurality of second scan lines, wherein, while the scan driving circuit provides the scan signals to the plurality of first scan lines, the driving controller outputs the clock signal in a normal power mode, and wherein, while the scan driving circuit provides the scan signals to the plurality of second scan lines, the driving controller outputs the clock signal in a low- power mode.” The U.S. Patent 11,798,463 does not expressly teach: a display device, which receives a mode signal from a host processor and displays an image. However, Noh teaches a display device, which receives a mode signal from a host processor and displays an image (FIG. 21, paragraph[0112] of Noh teaches according to embodiments, the host processor 1030 can perform various computing functions or tasks; the host processor 1030 may be one of an application processor (AP) that includes a graphics processing unit (GPU), a central processing unit (CPU), or a micro processor, etc; the host processor 1030 provides a control signal CTRL, and input image data IDAT to the display device 1050; and for example, the host processor 1030 may provide to the display device 1050 a mode signal SMODE that indicates a normal driving mode and frame data FDAT in response to the sense signal SSENSE indicating that the display device 1050 is not folded, may provide to the display device 1050 the mode signal SMODE that indicates a first partial driving mode in which the first display region is driven and first partial image data PDAT1 in response to the sense signal SSENSE indicating that the display device 1050 is folded such that the first display region is located in the front side and the second display region is located in the back side, and may provide to the display device 1050 the mode signal SMODE that indicates a second partial driving mode in which the second display region is driven and second partial image data PDAT2 in response to the sense signal SSENSE indicating that the display device 1050 is folded such that the first display region is located in the back side and the second display region is located in the front side, and See also at least paragraph[0113] of Noh (i.e., Noh teaches a host processor that provides a mode signal to a display device that displays an image based on a control signal and input image data)). Furthermore, U.S. Patent 11,798,463 and Noh are considered to be analogous art because they are from the same field of endeavor with respect to a display device, and involve the same problem of suitably driving regions of the display device that is foldable. Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to modify the system of U.S. Patent 11,798,463 based on Noh to have a display device, which receives a mode signal from a host processor and displays an image. One reason for the modification as taught by Noh is have a display device that prevents or reduces an image sticking caused by a degradation deviation (paragraph[0004] of Noh). In addition, it would have been obvious to one of ordinary skill in the art to remove the further limitations “a plurality of pixels connected to; signals that include a first clock signal and a second clock signal, wherein, while an operating mode is a multi-frequency mode,; wherein, in the multi-frequency mode,; wherein a hold frame of the multi-frequency mode includes a first section during which the first display area is driven, and a second section during which the second display area is driven”, since omitting the further limitations does not prevent the device from functioning properly, and the claim is in “comprising” format indicating other elements could be added. Moreover, any claims dependent on claim 15 in corresponding grounds of rejection are rejected based at least on same above reasoning.
Claim 1, and 2-7 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1, 2-5, and 8-9 respectively of U.S. Patent No. 12,217,660. Although the claims at issue are not identical, they are not patentably distinct from each other because the scope of the independent claims, mentioned above, are substantially the same.
The following is an example for comparing claim 1 of this application and respective claim 1 of U.S. Patent No. 12,217,660:
Instant Application
U.S. Patent No.
12,217,660
Claim 1
Claim 1
A display device comprising: a display panel including a plurality of first scan lines corresponding to a first display area and a plurality of second scan lines corresponding to a second display area; a scan driving circuit, which drives the plurality of first scan lines and the plurality of second scan lines in synchronization with a clock signal; and a driving controller, which outputs the clock signal,
A display device comprising: a display panel including a plurality of pixels connected to a plurality of scan lines and divided into a first display area which operates at a first operating frequency and a second display area which operates at a second operating frequency; a scan driving circuit, which drives the plurality of scan lines in synchronization with a clock signal; and a driving controller, which outputs the clock signal, wherein, while an operating mode is a multi-frequency mode,
wherein the scan driving circuit provides scan signals of a first operating frequency to the plurality of first scan lines and provides scan signals of a second operating frequency lower than the first operating frequency to the plurality of second scan lines, wherein, while the scan driving circuit provides the scan signals to the plurality of first scan lines, the driving controller outputs the clock signal in a normal power mode, and wherein, while the scan driving circuit provides the scan signals to the plurality of second scan lines, the driving controller outputs the clock signal in a low- power mode.
the scan driving circuit provides scan signals of a first operating frequency to first scan lines positioned in the first display area among the plurality of scan lines, and provides scan signals of a second operating frequency lower than the first operating frequency to second scan lines positioned in the second display area among the plurality of scan lines, wherein a hold frame of the multi-frequency mode includes a first section during which the first display area is driven, and a second section during which the second display area is driven, and wherein the driving controller has a control signal generator that outputs the clock signal in a normal power mode during the first section and outputs the clock signal in a low-power mode during the second section.
Independent claim 1 of the instant application teaches “A display device comprising: a display panel including a plurality of first scan lines corresponding to a first display area and a plurality of second scan lines corresponding to a second display area; a scan driving circuit, which drives the plurality of first scan lines and the plurality of second scan lines in synchronization with a clock signal; and a driving controller, which outputs the clock signal, wherein the scan driving circuit provides scan signals of a first operating frequency to the plurality of first scan lines and provides scan signals of a second operating frequency lower than the first operating frequency to the plurality of second scan lines, wherein, while the scan driving circuit provides the scan signals to the plurality of first scan lines, the driving controller outputs the clock signal in a normal power mode, and wherein, while the scan driving circuit provides the scan signals to the plurality of second scan lines, the driving controller outputs the clock signal in a low-power mode.” In addition, it would have been obvious to one of ordinary skill in the art to remove the further limitations “a plurality of pixels connected to; wherein, while an operating mode is a multi-frequency mode; wherein a hold frame of the multi-frequency mode includes a first section during which the first display area is driven, and a second section during which the second display area is driven”, since omitting the further limitation does not prevent the device from functioning properly, and the claim is in “comprising” format indicating other elements could be added. Moreover, any claims dependent on claim 1 in corresponding grounds of rejection are rejected based at least on same above reasoning.
Claim 8, 9-10, 12, and 14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 12, and 13-16, respectively of U.S. Patent No. 12,217,660. Although the claims at issue are not identical, they are not patentably distinct from each other because the scope of the independent claims, mentioned above, are substantially the same.
The following is an example for comparing claim 8 of this application and respective claim 12 of U.S. Patent No. 12,217,660:
Instant Application
U.S. Patent No.
12,217,660
Claim 8
Claim 12
A display device comprising: a display panel including a plurality of first scan lines corresponding to a first display area and a plurality of second scan lines corresponding to a second display area; a scan driving circuit, which drives the plurality of first scan lines and the plurality of second scan lines in synchronization with a clock signal; a voltage generator, which generates a first voltage and a second voltage in response to a voltage control signal; and a driving controller, which outputs the clock signal and the voltage control signal,
A display device comprising: a display panel including a plurality of pixels connected to a plurality of scan lines and divided into a first display area which operates at a first operating frequency and a second display area which operates at a second operating frequency; a scan driving circuit, which drives the plurality of scan lines in synchronization with a clock signal; a voltage generator, which generates a first voltage and a second voltage in response to a voltage control signal; and a driving controller, which outputs the clock signal, wherein, in the multi-frequency mode,
wherein the scan driving circuit provides scan signals of a first operating frequency to the plurality of first scan lines and provides scan signals of a second operating frequency lower than the first operating frequency to the plurality of second scan lines, wherein, while the scan driving circuit provides the scan signals to the plurality of first scan lines, a voltage difference between the first voltage and the second voltage is a first value, wherein, while the scan driving circuit provides the scan signals to the plurality of second scan lines, a voltage difference between the first voltage and the second voltage is a second value smaller than the first value, and wherein the clock signal is a signal that swing between the first voltage and the second voltage.
the scan driving circuit provides scan signals of a first operating frequency to first scan lines positioned in the first display area among the plurality of scan lines, and provides scan signals of a second operating frequency lower than the first operating frequency to second scan lines positioned in the second display area among the plurality of scan lines, wherein a hold frame of the multi-frequency mode includes a first section during which the first display area is driven, and a second section during which the second display area is driven, wherein a voltage difference between the first voltage and the second voltage during the second section is smaller than a voltage difference between the first voltage and the second voltage during the first section, and wherein the clock signal is a signal that swing between the first voltage and the second voltage.
Independent claim 8 of the instant application teaches “A display device comprising: a display panel including a plurality of first scan lines corresponding to a first display area and a plurality of second scan lines corresponding to a second display area; a scan driving circuit, which drives the plurality of first scan lines and the plurality of second scan lines in synchronization with a clock signal; a voltage generator, which generates a first voltage and a second voltage in response to a voltage control signal; and a driving controller, which outputs the clock signal and the voltage control signal, wherein the scan driving circuit provides scan signals of a first operating frequency to the plurality of first scan lines and provides scan signals of a second operating frequency lower than the first operating frequency to the plurality of second scan lines, wherein, while the scan driving circuit provides the scan signals to the plurality of first scan lines, a voltage difference between the first voltage and the second voltage is a first value, wherein, while the scan driving circuit provides the scan signals to the plurality of second scan lines, a voltage difference between the first voltage and the second voltage is a second value smaller than the first value, and wherein the clock signal is a signal that swing between the first voltage and the second voltage.” In addition, it would have been obvious to one of ordinary skill in the art to remove the further limitations “a plurality of pixels connected to; wherein, in the multi-frequency mode; wherein a hold frame of the multi-frequency mode includes a first section during which the first display area is driven, and a second section during which the second display area is driven”, since omitting the further limitation does not prevent the device from functioning properly, and the claim is in “comprising” format indicating other elements could be added. Moreover, any claims dependent on claim 8 in corresponding grounds of rejection are rejected based at least on same above reasoning.
Claims 15, and 16-18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 17, and 18-19, respectively of U.S. Patent No. 12,217,660 in view of Noh et al., U.S. Patent Application Publication 2021/0174716 A1 (hereinafter Noh). Although the claims at issue are not identical, they are not patentably distinct from each other because the scope of the independent claims, mentioned above, are substantially the same.
The following is an example for comparing claim 15 of this application and respective claim 17 of U.S. Patent No. 12,217,660:
Instant Application
U.S. Patent No.
12,217,660
Claim 15
Claim 17
An electronic device comprising: a display device, which receives a mode signal from a host processor and displays an image, wherein the display device comprises: a display panel including a plurality of first scan lines corresponding to a first display area and a plurality of second scan lines corresponding to a second display area; a scan driving circuit, which drives the plurality of first scan lines and the plurality of second scan lines in synchronization with a clock signal; and a driving controller, which outputs the clock signal in response to the mode signal,
An electronic device comprising: a display device, which receives a mode signal from a host processor and displays an image, wherein the display device comprises: a display panel including a plurality of pixels connected to a plurality of scan lines and divided into a first display area which operates at a first operating frequency and a second display area which operates at a second operating frequency; a scan driving circuit, which drives the plurality of scan lines in synchronization with a clock signal; and a driving controller, which outputs the clock signal in response to the mode signal, wherein, while an operating mode is a multi-frequency mode,
wherein the scan driving circuit provides scan signals of a first operating frequency to the plurality of first scan lines and provides scan signals of a second operating frequency lower than the first operating frequency to the plurality of second scan lines, wherein, while the scan driving circuit provides the scan signals to the plurality of first scan lines, the driving controller outputs the clock signal in a normal power mode, and wherein, while the scan driving circuit provides the scan signals to the plurality of second scan lines, the driving controller outputs the clock signal in a low-power mode.
the scan driving circuit provides scan signals of a first operating frequency to first scan lines positioned in the first display area among the plurality of scan lines, and provides scan signals of a second operating frequency lower than the first operating frequency to second scan lines positioned in the second display area among the plurality of scan lines, wherein a hold frame of the multi-frequency mode includes a first section during which the first display area is driven, and a second section during which the second display area is driven, and wherein the driving controller has a control signal generator that outputs the clock signal in a normal power mode during the first section and outputs the clock signal in a low- power mode during the second section.
Independent claim 15 of the instant application teaches “An electronic device comprising: a display device, which receives a mode signal from a host processor and displays an image, wherein the display device comprises: a display panel including a plurality of first scan lines corresponding to a first display area and a plurality of second scan lines corresponding to a second display area; a scan driving circuit, which drives the plurality of first scan lines and the plurality of second scan lines in synchronization with a clock signal; and a driving controller, which outputs the clock signal in response to the mode signal, wherein the scan driving circuit provides scan signals of a first operating frequency to the plurality of first scan lines and provides scan signals of a second operating frequency lower than the first operating frequency to the plurality of second scan lines, wherein, while the scan driving circuit provides the scan signals to the plurality of first scan lines, the driving controller outputs the clock signal in a normal power mode, and wherein, while the scan driving circuit provides the scan signals to the plurality of second scan lines, the driving controller outputs the clock signal in a low- power mode.” The U.S. Patent 11,798,463 does not expressly teach: a display device, which receives a mode signal from a host processor and displays an image. However, Noh teaches a display device, which receives a mode signal from a host processor and displays an image (FIG. 21, paragraph[0112] of Noh teaches according to embodiments, the host processor 1030 can perform various computing functions or tasks; the host processor 1030 may be one of an application processor (AP) that includes a graphics processing unit (GPU), a central processing unit (CPU), or a micro processor, etc; the host processor 1030 provides a control signal CTRL, and input image data IDAT to the display device 1050; and for example, the host processor 1030 may provide to the display device 1050 a mode signal SMODE that indicates a normal driving mode and frame data FDAT in response to the sense signal SSENSE indicating that the display device 1050 is not folded, may provide to the display device 1050 the mode signal SMODE that indicates a first partial driving mode in which the first display region is driven and first partial image data PDAT1 in response to the sense signal SSENSE indicating that the display device 1050 is folded such that the first display region is located in the front side and the second display region is located in the back side, and may provide to the display device 1050 the mode signal SMODE that indicates a second partial driving mode in which the second display region is driven and second partial image data PDAT2 in response to the sense signal SSENSE indicating that the display device 1050 is folded such that the first display region is located in the back side and the second display region is located in the front side, and See also at least paragraph[0113] of Noh (i.e., Noh teaches a host processor that provides a mode signal to a display device that displays an image based on a control signal and input image data)). Furthermore, U.S. Patent 11,798,463 and Noh are considered to be analogous art because they are from the same field of endeavor with respect to a display device, and involve the same problem of suitably driving regions of the display device that is foldable. Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to modify the system of U.S. Patent 11,798,463 based on Noh to have a display device, which receives a mode signal from a host processor and displays an image. One reason for the modification as taught by Noh is have a display device that prevents or reduces an image sticking caused by a degradation deviation (paragraph[0004] of Noh). In addition, it would have been obvious to one of ordinary skill in the art to remove the further limitations “a plurality of pixels connected to; wherein, while an operating mode is a multi-frequency mode; wherein a hold frame of the multi-frequency mode includes a first section during which the first display area is driven, and a second section during which the second display area is driven”, since omitting the further limitations does not prevent the device from functioning properly, and the claim is in “comprising” format indicating other elements could be added. Moreover, any claims dependent on claim 15 in corresponding grounds of rejection are rejected based at least on same above reasoning.
Potentially Allowable Subject Matter
Claims 1, 8, and 15 would be allowable if rewritten to overcome applicable double patenting rejection(s) and objection(s) indicated above, because for claims 1, 8, and 15 the prior art references of record do not teach the combination of all element limitations as presently claimed. In addition, claims 2-7, 9-14, and 16-20 would be allowable if rewritten to overcome applicable double patenting rejection(s) and objection(s) indicated above because for each of claims 2-7, 9-14, and 16-20, in light of their dependency on their respective independent claims, the prior art references of record do not teach the combination of all element limitations as presently claimed.
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure and include the following:
Na et al., U.S. Patent Application Publication 2016/0111055 A1 (hereinafter Na) teaches a display apparatus that includes a display panel and timing controller that determines a first driving frequency of a first display area based on first image data displayed on a first display area of the display panel, and determines a second driving frequency of a second display area based on second image data displayed on a second display area of the display panel.
Mori et al., U.S. Patent Application Publication 2017/0285817 A1 (hereinafter Mori) teaches a display device that lowers the update frequency of display content to suitably reduce power consumption.
Yoon et al., U.S. Patent Application Publication 2021/0027697 A1 (hereinafter Yoon) teaches a display device in which a circuit configuration of a scan driver is simplified, and power consumption is reduced by driving a partial region of a display panel.
Kim et al., U.S. Patent Application Publication 2022/0157250 A1 (hereinafter Kim I) teaches a display device with a scan driver that includes a driving circuit and a masking circuit, wherein the display device with the scan driver is capable of reducing power consumption of the display device and is operated in a multi-frequency mode to improve display quality.
Conclusion
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/ABDUL-SAMAD A ADEDIRAN/Primary Examiner, Art Unit 2621