DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending and examined.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of copending Application No. 18/131,600 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because they both recite limitations regarding an AI accelerator operating based on first, second, and third registers.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 8-10, 16-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 8,966,319 to Fai et al. (hereafter Fai).
Examiner’s notes: since each of the steps performed in FIG. 4 of Fai is instructed by processor(s)/microprocessor(s) and computer programs (see 10:57-12:21), performance of each step is seen as an AI operation.
Regarding independent claim 1, Fai teaches a memory device, comprising:
a memory array (see 10:10-11:61);
a controller configured to receive a command to enable the memory device to perform an artificial intelligence (Al) operation using data stored in the memory array (FIGS. 1 and 4: memory controller 116 receives commands and sets a flag in trigger(s) 126 to indicate if the NVM package has been instructed to perform an AI operation of collect debug information, see 9:7-21);
a first register configured to enable usage of an activation function for the Al operation (FIG. 1: for storing the flag in trigger(s) 126);
a second register configured to enable the memory device to operate in an artificial intelligence (Al) mode to perform the Al operation (FIGS. 1 and 4: trigger(s) 128 to determine if debug information should be collected or not in step 404, when they are used in combination with trigger(s) 126, see 5:1-13); and
an artificial intelligence (Al) accelerator configured to perform the Al operation using the data stored in the memory array (special purpose logic circuitry and hardware within the memory die to carry out the operation of collecting debug information).
Regarding dependent claim 2, Fai teaches a third register configured to define a resolution of an input of the activation function (e.g. triggers related to particular conditions within the memory device such as temperature, available voltage, particular memory address, see 7:50-8:5, which are seen as input of an activation function during collecting debug information).
Regarding dependent claim 3, Fai teaches a third register configured to define a resolution of an output of the activation function (e.g. trigger related to operational failures, see 7:50-8:5, which are seen as output of an activation function during collecting debug information).
Regarding independent claim 8, Fai teaches a memory device, comprising:
a memory array (see 10:10-11:61);
a controller configured to receive a command to enable the memory device to perform an artificial intelligence (AI) operation using data stored in the memory array (FIGS. 1 and 4: memory controller 116 receives commands and sets a flag in trigger(s) 126 to indicate if the NVM package has been instructed to perform an AI operation of collect debug information, see 9:7-21);
a first register configured to enable usage of an activation function for the AI operation (FIG. 1: for storing the flag in trigger(s) 126);
a second register configured to define the activation function for the AI operation (e.g. triggers related to particular conditions within the memory device such as temperature, available voltage, particular memory address, see 7:50-8:5, which are seen as input to define an activation function during collecting debug information);
a third register configured to enable the memory device to operate in an artificial intelligence (AI) mode to perform the AI operation (FIGS. 1 and 4: trigger(s) 128 to determine if debug information should be collected or not in step 404, when they are used in combination with trigger(s) 126, see 5:1-13); and
an artificial intelligence (AI) accelerator configured to perform the AI operation using the data stored in the memory array (special purpose logic circuitry and hardware within the memory die to carry out the operation of collecting debug information).
Regarding dependent claim 9, Fai teaches wherein the second register is configured to define a pre-defined activation function (e.g. triggers related to particular conditions within the memory device such as temperature, available voltage, particular memory address, see 7:50-8:5, which are seen as input to define an activation function during collecting debug information).
Regarding dependent claim 10, Fai teaches wherein the pre-defined activation function is at least one of: an identity function, a binary step function, a logistic function, a hyperbolic tangent function, an inverse tangent function, a softsign function, an inverse square root unit function, a rectified linear unit function, a leaky rectified linear unit function, a parametric rectified linear unit function, a randomized leaky rectified linear unit function, an exponential linear unit function, or a scaled exponential linear unit function (FIG. 4: such as identifying if triggers are set in step 406, OR if specified criteria are met in step 408, wherein the triggers are used in various logic operations such as AND, OR, and/or XOR of binary function, see 8:24-28).
Regarding independent claim 16, Fai teaches a method, comprising:
receiving, at a controller of a memory device, a command to enable the memory device to perform an artificial intelligence (AI) operation using data stored in a memory array of the memory device (FIGS. 1 and 4: memory controller 116 receives commands and sets a flag in trigger(s) 126 to indicate if the NVM package has been instructed to perform an AI operation of collect debug information, see 9:7-21);
enabling, at a first register, usage of an activation function for the AI operation (FIG. 1: via flag in trigger(s) 126);
enabling, at a second register, the memory device to operate in an artificial intelligence (AI) mode to perform the AI operation (FIGS. 1 and 4: via trigger(s) 128 to determine if debug information should be collected or not in step 404, when they are used in combination with trigger(s) 126, see 5:1-13); and
performing, at an artificial intelligence (AI) accelerator, the AI operation using the data stored in the memory array (via special purpose logic circuitry and hardware within the memory die to carry out the operation of collecting debug information).
Regarding dependent claim 17, Fai teaches identifying, at a third register, the activation function stored in the memory array used during the AI operation (e.g. via triggers related to particular conditions within the memory device such as temperature, available voltage, particular memory address, see 7:50-8:5, which are seen as input of an activation function during collecting debug information).
Regarding dependent claim 18, Fai teaches identifying, at a third register, a location of neurons in the memory array used during the AI operation (e.g. trigger related to operational failures, see 7:50-8:5, which are seen as output of an activation function to activate other activation function for collecting debug information).
Regarding dependent claim 19, Fai teaches identifying, at a third register, a location of an input of the AI operation in the memory array (e.g. triggers related to particular conditions within the memory device such as temperature, available voltage, particular memory address, see 7:50-8:5, which are seen as input of an activation function during collecting debug information).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-7, 11-15, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Fai in view of PGPub. 2002/0065646 to Waldie et al. (hereafter Waldie).
Fai teaches, as applied in prior rejection of claim 1, all claimed subject matter. Fai further teaches the debug operation is performed with program instructions encoded in an artificially generated propagated signal (see 10:57-11:15).
Regarding dependent claims 4-7, Waldie teaches a debug operation is performed with program instructions using various registers and triggers (see FIGS. 2-11).
Since Fai and Waldie are both from the same field of endeavor, the purpose disclosed by Waldie would have been recognized in the pertinent art of Fai.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to:
realize that registers are fundamental elements used to provide program instructions.
realize that, even though Waldie does not explicitly teach a [third] register configured to define a specific value as recited in each of claims 4–7, it is a matter of design choice to choose values that define the program instruction according to the user's preference.
Regarding dependent claims 11-15 and 20, see rejection applied to claims 4-7 above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM.
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September 15, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
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